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Software Development C++

Location:
Gainesville, FL
Posted:
June 16, 2024

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Resume:

Abha Singh

Gainesville, Florida +1-352-***-**** *******@***.*** LinkedIn GitHub

EDUCATION

University of Florida, Gainesville, Florida August 2022 – May 2024 Master of Science in Electrical and Computer Engineering GPA: 3.53/4.0 SRM Institute of Science and Technology, Chennai, India July 2014 – June 2018 Bachelor of Technology in Electrical and Electronics Engineering GPA: 3.64/4.0 TECHNICAL SKILLS

Programming: C, Python, C++, Embedded C, AUTOSAR, MATLAB/Simulink, SQL, MS Excel, Bash. HDLs & Protocols: Verilog, VHDL, CAN/CANFD, LIN, FlexRay, Ethernet, TCP/IP, PCIe, I2C, SPI, UART. Safety Standards: ISO 26262, UML (Unified Modeling Language), Unit Testing, Diagnostics, JTAG, Polyspace, ASPICE, MISRA C. Tools & Technologies: Git, Linux, Canalyser, Jenkins, IPG-Carmaker, Datalyser, Wireshark, QAC Handling, JIRA, Jenkins, Confluence. Certifications & Skills: Google Cybersecurity, Python Bootcamp, X86, ARM, Embedded Systems, DSP, Real Time Operating Systems. EXPERIENCE

Continental Automotive Group Bengaluru, India

Served as ESC Function Responsible for Hydraulic Booster Assist, Booster Performance, Failure Support, Ready Alert Brake, Rain Brake Assist, and Collision Mitigation Support for MKC2 and MK100 systems. Technical Specialist January 2021–July2022

• Single point of contact for ASPICE compliance at TCI, Bengaluru. Achieved >95% coverage in SWE.3 and SWE.4 ASPICE documentation for Continental Base Projects

• Authoring system level requirements (FRSR2) for customer specific changes. Further refined into software requirements (SRS3).

• Responsible for handling new customer requirements. Provide support for other team members by reviewing work products and supporting software release activities. Organized SW bootcamp at TCI, Bengaluru.

• Improved code quality and maintainability utilizing Misra C guidelines, raised code coverage and traceability from 70% to 90% through test-driven development and Agile practices. Associate Software Engineer December 2018 – December 2020

• Developed failure support for Nissin Electric Booster ECU, resulting in a 15% improvement in booster performance.

• Creating the simulation setup for HIL and preparing test specification against the function’s requirements.

• Identify software bugs during software execution and reporting to Software development team by using JIRA.

• Analyzed cross-functional dependencies, organized meetings to discuss the impact of cross-functional dependencies.

• Work closely with design, validation, and project management counter parts to meet the project timelines. Graduate Engineering Trainee July 2018 – November 2018

• Learned Vehicle dynamics. Demonstrated and coordinated quick learning skills with team members and completed mini project.

• Perform testing, and debugging for different mechanisms like parking brake, wiper mount assembly for control functions. Gas Authority of India Limited Auraiya, India

Electrical Engineer Intern May 2016 – July 2016

• Applied hands-on expertise to manufacture electrical machine, align with precise specification and transformer functionalities.

• Conducted in-depth analysis of 5 different existing tracks, actively debugging and rectifying faults for improved performance. PROJECTS

Intel DevCloud Utilization SYCL Programming, OpenCL December 2023

• Applied problem-solving skills to identify and rectify bugs, ensuring the successful execution of vectorized sequential code.

• Implemented OpenCL directives within custom kernels to enable multi-threading, maximizing hardware utilization. 1-D Time Domain Convolution using FPGA Xilinx Vivado, Modelsim, VHDL December 2023

• Designed and developed signal buffer, kernel buffer and the convolution pipeline and tackled metastability issues during Clock Domain Crossing using FIFO.

• Implemented a custom accelerator circuit in VHDL on the Zedboard to obtain convoluted outputs for a given input.

• Enhanced the circuit to obtain parallelism with a 14x speed upgrade, compared to the software implementation of the output. Timing Optimization (STA) on a custom circuit Virtuoso, Intel Quartus Prime May 2023

• Analyzed a custom circuit and optimized it to run at a higher frequency.

• Identified the critical path and applied different strategies to eliminate significant timing bottlenecks.

• Tested the design with a testbench to ensure that it works without errors.



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