Test Engineer Embedded Systems

YU MIAO

*** ****** ***** ******, ********** ***** C 469-***-**** **********@*****.***

SUMMARY

A highly skilled and results-driven electrical/electronic engineer, with extensive experience in developing ATE solutions for various complex RF SoCs such as WiFi, Bluetooth single-chip, high-performance analog devices. RF MEMS tuners, RF SOI switches. Hands-on experiences with OSAT vendors by designing the customized test platforms, planning production setups, etc. Defines the architecture for DFT, RF system hardware and software co- simulation, system verification, embedded systems, hardware and firmware development, and ATE tester development. Demonstrated capabilities in characterization, qualification, yield enhancement, and data analysis and reporting, as well as sophisticated RF and high-speed DAC board-level design. Familiar with wireless telecommunication standards. A self-motivated leader, who combines excellent communication and problem-solving skills with proven business acumen to consistently exceed expectations. TECHNICAL SKILLS

Design and Development Tools: Mentor Graphics Design Capture/DFTAdvisor, ModelSim, Cadence Design Entry CIS/Allegro, Protel, Altium Designer, Synopsys, Agilent ADS, MATLAB, Simulink, SPICE, DataPower, Galaxy Examinator, SmartTest IGXL, IMAGE, NI STS Software Bundle. Expertise on DVT Lab instruments such as oscilloscopes, vector network analyzers, signal generators, etc. Experience in Linux OS for IoT applications.

Programming Languages: C/C++, Pascal, Fortran, Visual Basic, MS Visual Studio, PERL, Python, Labview, LabWindow/CVI, TestStand, Assembly languages for Embedded Systems, VHDL, Verilog. EXPERIENCE

MORSE MICRO INC, IRVINE, CALIFORNIA

PRINCIPAL TEST ENGINEER, AUGUST 2022 – NOVEMBER 2023

Develop quad-site FT solution on Teradyne UltraFlex 12G MW test platform for MM6108 – Single-Chip IEEE802.11ah Wi-Fi HaLow Transceiver for Low-Power, Long-Reach IoT Applications, offload the product to EAG, and ASE-SGP.

Develop Octo-site FT solution on Teradyne UltraFlex 12G MW test platform for MM810X - Single-Chip IEEE802.11ah Wi-Fi HaLow Transceiver with built-in PA and LNA for Low-Power, Long-Reach IoT Applications. WISPRY/AAC TECHNOLOGY, IRVINE, CALIFORNIA

PRINCIPAL TEST ENGINEER, 2015-JUNE 2022

Develop quad-site FT solution on Teradyne Catalyst test platform for WS1040/1041/1042 – a four bank digitally tunable capacitor array, product qualification, characterization, and offload to UTAC Dongguan.

Develop quad-site FT solution on Teradyne Catalyst test platform for WS1050.2 w/ OTP – a three bank digitally tunable capacitor array, offload ATE solution to Carsem Malaysia.

Develop quad-site LCR based membrane prober solution for WS1021 w/OTP – a single bank digitally tunable capacitor array, support device characterization, qualification.

Develop single-site VNA-based membrane prober solution for WS1121 w/OTP- a single bank digitally tunable capacitor array.

Develop Wispry generic RF NI STS test platform for WS1040, WS1050.2, WS1021, WS1121, WS5310.

Work with OSAT vendors like UTAC, UNISEM, Amkor, JCAP, etc. to define test platforms for Wispry products, work with tester vendors like NI, Teradyne, Advantest, Chromas, Marvin Test, FormFactor, Keysight, R&S to configure test platforms.

Develop test evaluation boards for lab use.

WISPRY, IRVINE, CALIFORNIA

SENIOR TEST ENGINEER, 2014-2015

DEVELOP ATE SOLUTIONS FOR WS1050 – THREE BANK DIGITALLY TUNABLE CAPACITOR ARRAY

Support product qualification, characterization, ATE solution including quad-site FT test & dual-site wafer probing

Offload FT & probing solutions to UTAC Singapore. BROADCOM IRVINE, CALIFORNIA

SENIOR STAFF TEST ENGINEER 2012 – 2014

Develop ATE solutions for BCM4350/4354 -Single-Chip 5G WiFi IEEE902.11ac 2x2 MAC/Baseband/Radio with Integrated Bluetooth4.0 + HS and FM Receiver

design ATE loadboards on Utraflex as the following DIBs: PCIE FCBGA 3x/USB3 FCBGA 4x/DEBUG FCBGA 1x/WLCSP 3x/WLBGA 4x/.

design ATE loadboards on V93K as the following DIBs: PCIE FCBGA 3X/WLCSP 3X/WLBGA 3x.

responsible for Burn-in(digital&RF)/qual/HTOL/Characterization/customer return, and developed test programs

bring up digital tests for all package variants (PCE FCBGA IPA/DEBUG FCBGA IPA/WLCSP IPA/WLCSP EPA/ WLBGA EPA) on all reversions (A0/B0/B1/2C1/C2/2C2).

maintain all loadboards for development, help to test program release.

bring up test programs on V93K for PCIE FCBGA / WLCSP / WLBGA Yu Miao, Page 2

TEXAS INSTRUMENTS, Dallas, Texas

Senior Test Engineer, Technical Ladder, HSP-DC, 2010-2012

Developed a dual-site ATE solution on Verigy93000 for DAC34H84 (Quad-CH, 16bit, 1.25GPS DAC).

Continuously developed a dual-site ATE solution on Verigy93000 for DAC3484 (four-channel, 16bit, 1.25GPS DAC) and DAC3482 (two-channel, 16bit, 1.25GPS DAC).

Developed a Quad-site ATE load board on Verigy93K for DAC3174 (Dual 14-bit 500MSPS DAC).

Created a Quad-site ATE solution on Verigy93K RF for AFE7070 (Dual 14bit 65MSPS DAC with Quadrature Modulator). Earned recognition for this first RF + DAC implemented on Verigy93K in TI.

Led the spinout Quad-site ATE solution on Verigy93K RF for AFE7071 (Low-Power Integrated 0IF Transmitter).

Supervised one college intern.

Senior Test Engineer, Technical Ladder, Medical Group, 2007-2010

Developed a total test solution (FT/Probe) for AFE5804/5805/5806, fully-integrated, eight-channel, high-speed, 12/14bit, analog front-end devices for Ultrasound Imaging. Developed FPGA solutions for multi-channel high-speed ADC data capture on testers. The product received the Apollo Award from the HPA Group.

Created an ATE solution on VLCT-LPN for TL5500 (Low-Noise Pre-Amp for MRI).

Designed an FT solution on the Eagle Tester for TPS6XXX (Energy Harvest Power Management IC).

Developed a Probe solution on the Eagle Tester for TX734 (four-channel, three-level RTZ, +/-90V, 2A integrated Ultrasound Transmitter).

Created an FT solution on VLCT-RFI for CC1401 (Wireless Telemetry Medical Service RF Transceiver).

Supervised new hires on test developments with VLCT. Staff Engineer, Technical Ladder, Wireless Group, 2006-2007

Held responsibility for developing a new test technology for complex Digital Radio Process (DRP) based RF SoCs, building the team with technical leaders from multiple groups to meet test challenges in wireless product development.

Initiated a design for the test and manufacturing team to meet test challenges on leading-edge RF SoC products.

Developed a full system test solution on the VLCT RFI tester for WLAN RF SoC (IEEE 802.11a/b/g), a migrating Radioscope, from bench to VLCT.

Led a test-method improvement initiative. Assessed all RF projects in WTBU. Analyzed test solutions projects, identified issues, and helped teams resolve those issues.

Directed a bench and ATE integrated solution to improve test road-map development. Trained new hires to pick up projects. Led co-ops on research projects.

Managed the development of DFT strategy for a single-chip RF SoC, including IEEE802.11 a/b/g, Bluetooth, FM. Senior RF Product/Test Engineer, Wireless Group, 1999-2006

Drove leading-edge test solution development, developed new strategies for low-cost RF test platform improvement, developed complex RF modulation tests on ATE development, and directed RF Built-In Self-Test (BIST) development.

Served as project lead on Design for Test (DFT) for Reconfigurable Digital Radio (RDR) 1 - a DRP-based single-chip solution for 2G/2.5G/3G (GSM/GPRS/EDGE/WCDMA/TDS-CDMA). Developed a total solution across Tester Platform and system simulation and verification and design for test and test-method improvement.

Developed DFT for a single-chip for WLAN (802.11a/b/g). Developed a new test solution to test high-speed ADC and DAC up to 100MHz on VLCT. Developed a VLCT RFI test solution for 802.11, a band (6GHz) to replace the VLCT RFM solution, the first six GHz VLCT RFI solutions on production.

Developed a Quad site ATE solution for Island 2 on VLCT RFI X2.

Led the team to develop a full characterization solution for first DRP-based single-chip GSM phone. Developed new test methods for complex modulation tests.

Managed the development of a full-characterization solution on the Teradyne Catalyst RF tester for the first DRP-based RF SoC CMOS single-chip production device for Bluetooth, the first time to perform system-level tests on ATE.

Drove the development of a full-characterization solution on the A580 RF tester for test chips – the first two DRP-based RF SoC chips for Bluetooth. It was also the first DRP chip.

Led the development of an ATE solution for TRF2153/2154 and TRF92153/92154 on the Teradyne RF A580 tester.

Developed an ATE solution for Butterfly – a 900MHz RF transceiver on the Credence RF tester. ADDITIONAL EXPERIENCE

Test Development Engineer, SPG Group, 1997-1999. Served as a Team Leader on ATE development. Used the Teradyne A540 and A580 tester to develop an ATE solution for high-volume hard disk-drive chips. FORWARD SYSTEMS AUTOMATION INC., Arlington, Texas, Electrical Engineer, 1995-1997. Held responsibility for designing a customized PC-based ATE system and electrical system in handlers. Developed a driver and GUI for PC-based automatic test systems by using Visual Basic. Used LabWindow/CVI to implement IEEE-p849 RS-232 and SECS II Protocol for interface between handlers and the Teradyne A540 tester. Designed real-time software for IEEE-488 bus ATE and EG2001 wafer prober. Developed real-time software on Cognex vision system for lead inspection and text recognition. Developed a test system to detect small capacitance with Resolution of 1fF. Designed tester and handler interface for FSA integrated handler systems. Planned with production-supervised technicians and worked on field service.

NON-LINEAR SIGNAL PROCESSING LABORATORY, San Antonio, Texas, Research Associate, 1993-1995. Led the top-down design of an IC chip for a generalized stack filter that was featured with the real-time operation, using Mentor Graphics v8.4., QuickSim, VHDL, and Yu Miao, Page 3

Autologic for simulation and synthesis. Developed a simulation code for non-linear signal processing, the Neural Network, and “fuzzy logic.”

SHENYANG UNIVERSITY OF TECHNOLOGY, Shenyang, China, Project Leader, R&D Institute, 1990-1993. Held responsibility for designing and developing robotic sensory systems. Managed modeling, specifying and partitioning the entire system. Directed electronic and mechanical design. Coded real-time modules for Intel8051 and X86 embedded subsystems, using Turbo C and assembly languages. Implemented HDLC protocol for STD bus real-time embedded system. MECHATRONICS R&D INSTITUTE, Shenyang, China, Project Engineer, 1987-1990. Designed and developed real-time embedded automatic test and control systems using Z80, Intel8051, 68HC11, and X86 microprocessors. Designed GUI software for PC-based test and control systems, using Turbo C and Pascal. Developed GPIB-based ATEs and STD bus-based embedded systems. Developed instrumentation and data management systems. Implemented a PC-based instantaneous telecommunication system, using the TMS32020 DSP board.

SHENYANG UNIVERSITY OF TECHNOLOGY, Shenyang, China, Lecturer, 1987-1993. Lectured on DSP, embedded systems, digital circuits, and technical English. Supervised undergraduate students on projects. EDUCATION

UNIVERSITY OF TEXAS, San Antonio, Texas, M.S.E.E., DSP Applications, 1997 SHENYANG UNIVERSITY OF TECHNOLOGY, Shenyang, China, M.S.E.E. - Electrical Engineering, 1987; B.S.E.E. - Electrical Engineering

PUBLICATIONS AND AWARDS

Yu Miao, Elida de Obaldia. “A New DFT/DFM Paradigm for Testing Complex RFICs” International. Mixed-Signal Testing Workshop, June27-29, 2005, Cannes, France.

Yu Miao, David Bement. “Characterizing Hard Disk-Drive Thermal Asperity Detection Circuitry with the VHFAWG, HFDIG, and HSD50, TUG 1999.

Yu Miao, Liz Vigrass, Shawn Smith, “On-Board FIFO Memory Module for High-Speed Digital Sourcing and Capture To/From Device Under Test (DUT), Using a Clock From DUT." Patented, October 2, 2006. In 2005, promoted as a Member of the Group Technical Staff (MGTS) at Texas Instruments. LANGUAGES

Fluent in English and Chinese.

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