Security Clearance Mixed Signal

Anna M. Burns

Cell: 512-***-****

ad5twr@r.postjobfree.com

QUALIFICATIONS SUMMARY

22+ years of experience in the layout of CMOS and Bi-CMOS designs with focus on analog, mixed signal and custom designs. Experience in floor planning, layout, chip finishing of complex circuits.

Circuits worked on include and not limited to PLL’s, Input-Output Buffers (IO Buffers), bandgap reference circuits, memory units as well as integration of routed database with custom designs and verification.

Experience in reading and interpreting DRM for pertinent technology, and visualizing the rules involved. Some of the technology nodes worked on include 90soi, 65soi, 45soi, 35soi, 22soi (soi- silicon on insulator), as well as bulk technology 28hpm,& 28tfs Experience in reading and interpreting files for troubleshooting and debugging.

Experienced with matching techniques such as common centroiding, interdigitating, mirror symmetry and the use of dummies. Matching of current mirrors, differential pairs, amplifier stages, resistors, capacitors and bi-polars.

Experienced with shallow trench isolation techniques, well proximity, voltage management, auto route.

Linux Operating System

DOE security clearance

PCB’s

TECHNICAL SKILLS

Layout Tools: Virtuoso (v 6.1.5), VirtuosoXL (v 6.1.4), Virtuoso Schematic editor

Verification Tools: Calibre, Assura, Hercules, Dracula, DIVA.

Version Control: Synchronicity, Versic, Perforce

Process Technologies: TSMC and Global Foundries 28nm, IBM 0.18um,TSMC 0.6um, 0.35um and 0.18um Deep Nwell CMOS, TSMC 0.5um BICMOS.

Operating Systems: Solaris, Unix, Linux, Windows CE.

Layout Techniques: Common Centroid and/or Interdigitation techniques and dummies for precise matching of differential input pairs and current mirrors. Minimization of RC parasitics by optimizing wire lengths and widths. Use of guard rings and substrate rings for isolation and awareness of ‘latch-up’ issues by adding substrate contacts where necessary, etc.

Circuit Specialties: Amplifiers, differential amps, plls, charge pumps, oscillators, bandgaps, switched capacitor networks, various references, main bias and clock blocks, high speed pads, pad rings. Various low-power applications were also utilized. Experience with mostly customer oriented production wafers and also circuits for ‘test-chip’ production. Familiarity with some memory interface cells.

Communication Skills: Very thorough lines of communication with circuit designers and fellow layout designers, producing an ability to confidently work independently or within a team environment. Will examine schematics very closely and bring any questions or concerns to the circuit designer as needed. Very high attention to detail is one of my strengths.

WORK HISTORY

SANDIA NATIONAL LAB (Direct), Albuquerque/NM Oct. 2015 – Present

Principal Layout Designer

IBM32SOI

Layout and verification of large shift register blocks for test chip Built and verified pad ring and logic for small test chip

CMOS7

Built silicon interposer to connect & route a 3D stacked focal point array. Provides power & signal distribution to a 3x3 array of stacks which contain a read out integrated circuit (ROIC) layer &

digital signal processing layer. This contains no active components & is being developed at Sandia to utilize a new thick metal process stack to accommodate high currents.

IBM45SOI

Layout and verification of neutron generator, bottom up to chip level. Pad frame, amplifier, DAC, Bandgap,etc

CMOS7

Built numerous chips including pad core, core logic, analog & digital blocks. All completed before due dates.

Built and verified from bottom up numerous blocks: amps, AGC, voltage multiplier, PLL, comaparator, thermal sensor, many bandgaps, bandgap switches, buffers, amplifiers, current mirrors, DAC, refgen

CMOS8

Built pad blocks with logic, 3 stage cascode block, output buffers, opamp, oscillator

Freescale Semiconductor (Direct) Feb 2013 – Oct 2015

Sr. IC Layout Engineer

28hpm tsmc technology

Layout and verification of high speed PLL and all sub blocks. VCO,filter, vco_delay, charge_pump, current_scaler, test_mux, current_scaler_decode, test_divider, clk_buffer.

28tfs tsmc technology

Layout and verification of charge pump low volatage comparator

Layout ad verification of mv Bandgap

40/55 nanometer bulk technology

Layout and verification of pll, vco, clk buffer, test divider, current scaler, regulator amp, bandgap,

level shifters, anmux, op amp, current mirrors, adc(analog to digital converter), charge_pump, bandgap, bandgap_ref_therm, bandgap_trim,vdet_ls, input_ls,comparator, sc_amp_comp_teleamp, ref_generator, RC_filters, top level large block to tape out.

Everspin Technologies (Contract) Sept 2012 – Jan 2013

Sr. IC Layout Engineer

90 nanometer bulk technology

Layout and verification of multiple charge pumps, high speed and mock, class ab buffer, programmable high speed oscillator, numerous current mirror blocks, numerous bias circuitry, as well as chip level integration of large blocks.

Freescale Semiconductor (contract) April 2012 – July 2012

Sr. IC Layout Engineer

* 90 nanometer 6mtl technology

* Layout and verification of high voltage op amp, high voltage rc filter, comparator, levelshifter bank, clkgen,

bufbias, ibias, core.

Vitesse, contract Sept 2010 - Jan 2011

Layout and verification of PLL in 65 nanometer technology.

Layout and verification of rgmii (ring test structure for premature aging of devices)

TSMC cmos65

IBM, Contract March 2010 - August 2010

Layout and verification of Relay Buffers, Sector Buffers, Skew Sense, DC Sense in 35 and 22 nanometer

17 metal stack soi technology . Proficient in debugging and reading files for verification due to no interactive verification tools.

Freescale Semiconductor, Contract 2005 - 2009

Senior Layout Designer, Networking Group

SoI technology,10 metal stack

Responsible for the layout of phase locked loop (PLL), IO BANKS and RINGS, and SGPC TESTCHIP

Incorporated several commonly and widely used techniques of common centroiding, interdigitating, and matching

differential inputs for the analog circuit of the PLL.

Worked closely with the PLL designers to achieve a robust power grid, and well matched capacitors throughout the design.

PLL:

Complete custom layout and verification of opamp, opamp bias circuit, comparator, adjustable CAP banks for input A/D converter, clocks, switches, ands, nands, nors, ors, invertors, complex gates, buffers, delay chain, vco, muxes, op_amp, receiver, latches, precision thermal sensor based on band gap reference, high k MIM caps for analog and mixed signal. Editing of netlists for verification purposes, tweaking and building schematics, creation of numerous release libs.

IO BANKS and RINGS:

Complete and custom layout and verification of high speed DDR IO Circuit: output stage, level shifters, on die termination, receivers, and associated control circuits.

SGPC TESTCHIP

Responsible for placing pad cells and design collaterals into a design testchip

Semtech Semiconductor, direct hire/site closure 2003 - 2005

Senior Layout Designer for top level floor planning, layout, verification and tapeout of test chip in high voltage, twin tub technology polarfab foundry, pbc4 (Bi-CMOS) process

Layout and verification of analog blocks and some custom digital designs.

Layout and verification of pads, pad logic and esd.

Bypass circuits, biasing circuits including centroiding to set up bias current, instrumentation amp, output buffers, input buffers, clamping circuits, switches, coupling capacitors, pmu, centroiding of diff pairs.

Cypress Semiconductor, direct hire/site closure 1998 - 2003

Senior Layout Designer for analog and flash memory macro blocks.

Complete custom layout and verification of digital blocks, macro blocks and standard cells

Complete custom layout and verification of analog blocks.

Chip level layout, verification and tapeout

2.5GHz Serial Input, 2.5GHz Serial Output, Phase Detector, Charge Pump, Op-AMP, Loop Filter, VCO, high speed logic, full speed output buffer (w/ resistor matching blocks, main CMOS output structure, predriver stagger turn on), high speed output buffer (w/ large P-FET current source with P-FET differential output gate), band-gap, standard cells, phase picker, base cells (w/ current sources, current source switches, bipolar switches, resistor loads), logic cell configurations from base cells (AND, OR, XOR, D-FF, D-Latch, 2:1 Muxes), receiver blocks, phase selector, phase detector, phase blender block.

Crystal Semiconductor, IC Layout Designer, direct hire 1996 - 1998

Chip level layout and verification

Complete custom layout and verification of dual port, low power rams from the bit cell up

Layout and verification of pad logic from the diffusion up (hand built diodes), pad rings, custom cells, standard cells, developed numerous pad and pad ring libraries.

Motorola, IC Layout Designer, direct hire 1994 - 1996

Layout and verification of pad logic, custom cells, and control logic

EDUCATION

Austin Community College, GPA: 3.85 1994

-Associate, Applied Science in Engineering Design Graphics w/ emphasis in I.C. Layout Design

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