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Design Engineer Rtl

Location:
Phoenix, AZ
Posted:
May 09, 2024

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Resume:

**** * **** ****

Phoenix, Arizona *****

602-***-****

*******@*****.***

DAVID COTE

Career Objective

To secure a position where experienced contributions add immediate value and acute learning drive career advance.

Experience

Canaan Creative—Phoenix, AZ June 1, 2022—November 30, 2023

Principal RTL Design Engineer

●RTL design owner of LPDDR{4,4x,5} RiscV memory controller for ASIC SoC targeting AI-centric end products

Capgemini/Facebook/Meta—Phoenix, AZ June 2021—May, 2022

Principal RTL Design Engineer

●RTL design owner of Triangular Solve Engine with pipelined parallel floating-point accelerators targeted for next generation Oculus VR ASIC implemented in 5nm Samsung process technology

Honeywell—Phoenix, AZ November, 2020—May, 2021

Principal Semiconductor Engineer

●Created UVM random testbench environment to demonstrate robust immunity to a wide range of transient noise events

●Completed testbench scoreboard matrix demonstrating correct FPGA behavior across thousands of unique testpoints

●Presented verification results to Boeing as well as participate in weekly customer meetings on flight control systems

●Completed complex task of formal verification for legacy netlist without synthesis guidance svf which I created manually

Mercury Systems—Phoenix, AZ November, 2019—October, 2020

Principal FPGA Design Engineer

●FPGA design of secure SSD architectures for mission critical terrestrial and space applications

IBM Microelectronics—(Acquired by GlobalFoundries) Contract via Encore Semi Phoenix, AZ January, 2015—November, 2019

SerDes Design Engineer

●Physical implementation owner of 112Gbps LR/XSR SerDes blocks in TSMC 7nm Cadence innovus flowtool

Owner of synthesis timing closure/signoff of LR and XSR SerDes blocks pre/post physical design

●Hardware lab bring up of 112Gbps SerDes core implemented in GF 14nm process technology

Wrote Lua algorithms and Python BER eye-diagram code for 112Gbps core and FPGA hardware verification

●RTL design owner of 112Gbps SerDes RxLinkLogic algorithms including Mueller-Muller CDR, 32-tap FFE, CTLE/peaking implemented using Cadence tool flow in GF 14nm with interface to Xilinx FPGA that included Reed-Solomon FEC, PAM4 pattern generator and checker implemented using Vivado tools

●RTL design of Dynamic Data Centering Rx algorithm for 56Gbps products in 14nm GF process technology

●Created Carry-Save Adder models at higher-level of abstraction significantly reducing simulation time

●Wrote testbench code in systemVerilog for individual ADC, LTE, DFE, FFE and CDR blocks as well as system-level rxCoreLogic testbenches to verify both the 112Gbps ASIC and FPGA implementations

Intel—Chandler, AZ October, 2013—October, 2014

Component Design Engineer

●Contributed to the 2nd Generation Fuse Controller Chassis IP including design/documentation updates and script/tool infrastructure creation improving automation, efficiency and quality of IP deliverables to product teams

Intel—Chandler, AZ April, 2011—October, 2013

Component Design Engineer

●Design owner of SerDes Tx High Speed Serial I/O RTL written in System Verilog in Intel 14nm process

●Created UPF solution for NLP power-aware simulation and synthesis of multiple power-gated logic partitions

●Created synthesis constraints for multiple clock domains meeting timing requirements up to 3GHz using Primetime STA and regression testing GLS with back-annotated SDF

●Experience with a variety of validation tools including VCS/DVE, Verdi, Lintra, Spyglass, CDC, Fishtail, LEC

●Authored TX Logic Architecture Specification, Test Plan and whitebox assertions

Intel—Chandler, AZ December 2010—April 2011

Design/Verification Engineer

●Verified complex media SoC design blocks using OVM on System-Level Emulation Palladium targets

●Created and verified new complex top-level media SoC IP block configuration using OVM test environment

Intel—Chandler, AZ May 2010—December 2010

Digital Design Engineer

●Designed massively parallel vector memory controller including load/store pipeline to reconfigurable systolic array of compute engines, aggregation cache and arbitration protocol for three different split transaction bus interfaces

Freescale—(formerly Motorola Semiconductor Products Sector)—Tempe, AZ 2005—2007

Senior Staff Technologist

●Created 68K/ColdFire core and platform RTL deployments for successful IP licensing with customers

●Hosted webinar for Freescale’s V2 ColdFire core platform IP available licensing @ ip-extreme.com

●Designed reusable testbench infrastructure deployments enabling seamless verification by customers

●Developed RTL build, sim & synthesis scripts (Synopsys/Cadence front-end flows) deployed with soft-IP

●Authored technical specifications required to integrate licensed IP with customer ASIC/SoC products

Motorola—Tempe, AZ 2004—2005

Staff Digital Design Engineer

●Technical manager of 5 direct report engineers

●Individual design contributor of reusable core-agnostic Standard Product Platform (SPP) blocks implemented in high-volume automotive and consumer electronic SoC products

Motorola—Tempe, AZ 1998—2004

Senior Microprocessor Design Engineer

●Designed instruction result forwarding optimization within the Operand Execution Pipeline (OEP) of V4 ColdFire Embedded Core products

●Designed reusable byte-sliced datapath structures to optimize synthesis implementation within 64-bit superscalar micro-architecture of V5 ColdFire Core products

●Performed extensive performance analyses over the years using EEMBC, customer and internal application code to benchmark competitive advantages of specific ISA solutions (68K/CF, ARM, PowerPC) versus competitors, e.g., MIPS— targets included core architectural models, ISS, Verilog and silicon

●Developed lint program, written in Perl, which verifies all Verilog source design files comply with reuse standards created by Motorola SRS and ColdFire design team

Motorola—Tempe, AZ 1995—1998

Embedded SoC Design Engineer

●Technical lead and project manager of imaging and storage SoC project developed for Iomega Jazz product delivered on-time and production ready 1st silicon met performance/cost/business goals

●Successful design and integration of a configurable serial interface module which serviced a range of customer protocols and requirements

Motorola—Tempe, AZ 1991—1995

MC68060 Design Verification Engineer

●Design architect of MC68060 microprocessor verification platform implemented in Verilog to provide the simulation infrastructure during 060 MPU development, then rapid prototyped into FPGA, and ultimately placed/routed into a high-performance PCB implementation used for silicon evaluation/debug

Edge Computer—Scottsdale, AZ 1985—1991

Senior CPU Technician/Engineering Aid

●Worked closely with CPU architects to create successful verification methodologies for proprietary CPU micro-mainframe (binary compatible 68K ISA)

Education

DeVry Institute of Technology Phoenix, AZ

●Bachelor’s Degree in Technical Management 1995—1997

DeVry Institute of Technology Phoenix, AZ

●Associates Degree in Electronics Engineering 1982—1984

Core Competencies

RTL Design, VHDL, SystemVerilog, Testbench Design, High-Speed SerDes Equalization Algorithms, CPU, DDR Microarchitectures, Lua, Python, Perl, C/C++ Firmware, ARM, X86, 68K, PowerPC and ISA’s, mixed signal, Matlab, coverage tools, assertions, LEC, ATPG, Primetime/Tempus STA, DFT, multiple clock domains, power/clock gating, low-power UPF, Linux, PCB design/layout/route, FPGA, GLS/SDF, performance modeling, Visio, MS-Office, FrameMaker



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