Senior Design Verification Manager

Victor Sutan

San Jose, CA

415-***-**** / ******@*****.***

• Accomplished ASIC development leader with 18 years of ASIC development cycles in Digital Design and Verification, including 9+ years of successfully leading and managing Design Verification teams through 7 different tape-outs.

• Adept at navigating the intricacies of cross-functional collaboration between Digital, Analog, Physical Design, Software and Validation teams.

• Experiences with ASIC projects tape-out in Graphics, SOC, Fingerprint, and Motion Sensor chip.

• Experiences with ARM M0+ and M4 over multiple projects.

• Proven track records in managing project schedules, identifying process improvements, and driving methodology enhancements to optimize efficiency and quality.

• Fluent in English and Indonesian, and conversational Mandarin. TDK Invensense - San Jose, CA

Sr Design Verification Manager Oct 2019 - Present

Responsible of managing and leading the Design Verification (DV) team to execute high quality RTL verification on schedule. Engage in discussions and reviews concerning architecture, micro-architecture and feature implementation. Create verification plans from the specifications and in coordination with architects. Involved in day to day DV activities (Test bench bring up, debug session, model bring up, etc). Manage bug tracking and close coverage. Hiring and staffing DV engineers in support of program needs. Led the DV team in the post-Silicon bring up and debug effort. Collect and track deliverables/report from the team. Report the DV progress to the management and the cross functional team. Align the DV team with the validation and software team for the FPGA need.

Selected accomplishments:

• Develop and implements the strategic plans for the verification team to keep up with the market and products demand. Defined the strategy to improve the time to verification complete with the block level verification and tool improvement.

• Guide and influence the Digital team in navigating long term architecture improvement (such as RISC-V core scoping) and flow improvement with the cross functional team.

• Oversee the DV team execution over multiple motion sensor projects. Manage the DV leads across different blocks, subsystems and SOC level, across multiple timezones.

• Guided the DV team through challenges and obstacles. Led a team of 6 DV engineers to turn around a critical IP and pulled schedule in by 2 months. Led the verification of the new Round-Robin Digital Satellite block. Revised and debugged the SystemVerilog constraints (based on the algorithm provided by the Design team) to reduce the illegal scenarios by 40%.

• Define and continuously improving the verification methodology through lesson learned, such as the checker activation scheme, signal path verification, checklist, block and SOC level testing. Summary

Work History

• Spearheaded and launched many widely adapted process improvement flows such as Design verification checklist, JIRA tracking guidelines, JIRA automation, Verification Plan template, and lesson learned methodology.

• Initiated and guided the evaluation effort for an alternate Formal tool (Yosys) in order to introduce formal verification to the methodology that could save the company at least $100K / license.

• Led and managed the team to evaluate the Questa simulator, as an alternative to the Xcelium simulator, to explore the possibility of increasing the regression license counts for a similar cost. Created the metrics, track the evaluation progress, and enabled the team and ensure the issues reached the correct owners.

• Led and deployed the new requirement tracking flow to improve traceability and reduce scope creep. Developed the demo for the CMOS team to reduce the tool adoption time.

• Manage the budgets for the verification team, including team assignment, team growth projection, and negotiating the SOW with the contracting company for the past 5 years. Successfully retained the core contractor team for the past 8 years.

Sr Staff Verification Engineer Oct 2016 - Sep 2019 Participated in architecture, micro-architecture and feature discussions and reviews. Define and develop test bench components using UVM and SystemVerilog. Create and execute the block level and SOC level verification plan. Manage subsystem DV team.

Selected Accomplishments:

• Led and managed the Digital Verification team (36 engineers) on a critical customer-facing project to ensure on-time delivery and high-quality Tape-out. Directly Responsible Individual (DRI) for the Design Verification team.

• Identified an issue with the SRAM current with the cross-functional team, and reviewed the issues and solution with the SRAM Vendor to ensure quality fixes for the next stepping. Created, and tested the workaround to unblock the Silicon Validation team.

• Collaborated with the cross-functional teams to tune the Fingerprint algorithm on different applications and packaging, leading to the productization of 2 Chips.

• Piloted Jenkins-based regression manager to improve regression performance and tools, which were widely adopted as the main Digital team’s methodology.

• Defined the methodology to more efficiently plan and track the Digital Verification team’s execution through JIRA, which became the base of the automated reporting tool for the Digital team.

• Brought up the test bench, with the voice BFM, and set up the compiler for the onboard processors, ahead of the planned schedule, and pulled in the project execution.

• Guided the Digital and Software team to create and tune the power scenario to improve power efficiency. Staff Verification Engineer June 2014 - Sep 2016

Defined test plans for unit-level and SOC level verification. Designed and implemented test benches and verification environment. Developed and debugged the directed and random tests. Mentor and guide the work of junior engineers. Code and analyze coverage to meet product quality requirements. Selected Accomplishments:

• Redesigned the legacy timers scoreboard for scalability which reduced the TB development time by 10% across the project.

• Created scripts to improve the scalability and reusability of the DV env and regression, resulting in maintenance improvement from 1 week to 1 day.

• Took the initiative to rewrite the firmware test sequences to use a base library with a variety of commonly used functions, allowing more lucid codes, and preventing users from recreating existing functions. Intel - Folsom, CA and Hillsboro, OR

Senior Verification Engineer Oct 2010 - Apr 2014

Defined test plans for unit-level and SOC level verification. Designed and implemented test benches and verification environment. Developed and debugged the directed and random tests. Mentor and guide the work of junior engineers. Code and analyze coverage to meet product quality requirements. Selected Accomplishments:

• Led the validation methodology for the Digital LDO block. Created SystemVerilog assertions that caught many of the firmware’s LDO programming bugs.

• Verified the concurrency traffic and the Content Protection Mechanism between the Graphics IP, the Video IP, and the memory.

• Successfully integrated an in-house automatic regression tool into the Multimedia environment, removing the need to run 14 test lists manually.

Component Design Engineer June 2006 - Oct 2010

Delivered a quality RTL as part of the Integrated GPU team. Conduct the IP level verification on the GPU IP. Run and debug emulation result.

Selected Accomplishments:

• Delivered a quality RTL design with 60% architectural changes from the previous project.

• Improved the validation by creating a standalone test bench, which increased the validation coverage by 20%.

• Led and collaborated a late design change with the power team, that saved approximately 200mW.

• Drove LEAN methodology, and educated the Graphics team on the process.

• Design Verification Tools and Methodology: Verilog, SystemVerilog, OVM/UVM, FPGA Emulation.

• Interface Protocol: SPI, I2C, AHB, APB, DMA.

• Program Management: Microsoft Projects, JIRA, Confluence, Trello, and Kanban System Design I.

• File Management System: Git, SOS, Perforce.

• Scripting Language: Perl, Perl-tk, Unix, Makefile, Python, Jinja2, SQL.

• Tools: Jenkins, FastProject.

Columbia University - New York, NY Sep 2004 - Dec 2006 Master of Science, Computer Engineering

University of Stony Brook - Stony Brook, NY Sep 2000 - May 2004 Bachelor of Engineering, Computer Engineering, Graduated Magna Cum Laude Recipient of the Interdisciplinary Biomedical Research Program Fellowship Key Skills

Education

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