Wang, Chi-Hung(Joe)

*** * ******** *****, ***** Park, TX 78613.

H: 512-***-****/M: 408-***-****. Email: ad5bg5@r.postjobfree.com

Career Summary:

•A proven problem solver, game changer and leader in software industry.

•Accomplished five leading software products for two major consolidated IC design automation companies; part of the reasons lead into the top three acquisitions in design automation history.

•Solid training in front-end/back-end/full-stack/cloud computing software designs. Contributed in real-life development for industry leading data visualization/automation/server products/flows.

•Pioneer in solving IC/device-level placement/routing/floorplanning automation/optimization/timing/verification/geometrical computation/SOC/CTS/Scan Chain/BSRG/Low Power/Synthesis/simulation problems for standard cell/block/analog/mixed signal layout designs.

•With thorough understandings in various areas and software design patterns in IC design flow, networking, client/server, big data management/visualization/mining in business software, AI/ML algorithms/techniques; ready to take the next chapter of challenges.

Skills:

•Expertise in the following areas :

•Data structures and computer algorithms.

•Front-end/back-end/full-stack development using Java/JavaScript/React/Spring Rest/Spring Boot/Ruby tools/Redux/Redux-saga/node/HTML/Json/XML/GitLab/IntelliJ/Gradle/

Electron/Selenium/Jasmine/Enzyme/Junit/CUDA/Docker/Jsoup/AWS/Kubernetes/GCP/Azure/Tableau Cloud on Windows/Mac platforms under Agile/Scrum/CI/CD development methodology.

•Complex algorithm-extensive software projects with C/C++/YACC/Python/Ruby/Matlab/QT/Tcl/Skill/csh/bash/perl/awk in Unix/Linux/Perforce/Coverity/Purify/ccollab/valgrind/asan/rbt environment and industry standard bug reporting/code review systems.

•Internet programming using Client/Server/Micro service/REST api in IPC/HTTP/gRPC protocols.

•Distributed processing, IPC, multi-threading/SIMD CUDA programming.

•Numerical analysis, computational software, regressions, constrained pre-conditioned large sparse matrix linear/non-linear optimization or ML solvers.

•Enterprise relational databases, cloud database and connectors, SQL applications.

•Machine learning, AI technologies and infrastructures, NumPy, MatLab, PyTorch.

•Business data visualization. Tableau tool/flow development.

•GUI/graphic ghosting coding.

•IC design netlist translation, pre-processing, format exchange/flow integration/extraction between LEF/DEF/EDIF/SDF/SPF/CDL/Spice/YAML/Verilog/database/internal netlist/constraint parsing and generation/library mapping.

•EDA logic/physical database cores/interfaces, including Cadence CDBA, OpenAccess, Magma Titan, Talus Bedrock, Synopsys Milkyway, Innovus DB.

•Strong desire and quickness to learn. A teammate with a can-do attitude, high energy, detail-oriented. Stellar communication skills.

•Ability and flexibility to work and communicate effectively in a multi-national, multi-time-zone corporate environment.

Professional Experiences:

Software Architect, Cadence Design Systems, Inc. Sep 2022 – Present

•Working on the latest Innovus SOC distributed optimization product, which uses multi-threading/multi-machine architectures like LSF/Client/Server/Socket/File Synching/fork/threading to build a flow that leverages all features in Innovus to optimize SOC designs to satisfy timing/power/area/density/congestion constraints. Debug/analyze/identify issues in complex flows including floorplaning, partition, placement, routing, extraction, static timing analysis, cts, optimization, density, power analysis, inter-process communication, cloud computing, primarily in TCL/C++/csh on Linux systems. Learned and fixed key bugs/flow-related issues/performance bottlenecks that few others can identify. Improved several key components’ performances by more than 30%, reduced the disk space usage by 90%.

Lead Software Engineer, Salesforce(Tableau), Sep 2019 – Sep 2022

•Worked on Tableau data prep and security-and-sharing products, applied modern front-end/full-stack technologies in big data/visualization flow using Java/React-JavaScript/TypeScript/Redux/Rest on Electron/IntelliJ platforms. Reduced assigned defects/stories by 100%, created new key features that cover the entire flow and significantly simplified usage model, welcomed by the customers right away. Quickly mastered modern software development skills in client/server/cloud environment. Had solid involvement in data visualization/flow/user authentication for various levels of real-life business software development.

•Implemented practical features like auto-updater which can automatically guide users to install the most up-to-date releases in multi-language platforms in a SAAS/cloud environment in a timely manner.

•Masterful for various software testing/regressions/unit test methodologies like canary tests, Selenium, JUnit, Jsoup; heavily involved in AWS kubernetes/docker and other Cloud platforms.

R&D engineer, Senior Staff, Synopsys Design, Inc. Feb 2012 – July 2019

•Accomplished the Placement Assistant product in Custom Compiler by integrating tools/features/flows from 4 leading companies using state-of-art coding/algorithmic and data flow skills; coded in C++/Python/YAML/S-expression/TCL/QT to resolve modern placement problems for 7 to 10 nm technologies. Went through 10+ release cycles.

•Continued to enhance the AVP product that I authored, evolved it into the core engine for Placement Assistant. Made it adapt to the Helix/Custom Compiler hierarchical design flow. Used threading technology and distributed computing to speed the placer by a magnitude of 10X. New genetic algorithms made it output multiple optimized solutions.

•Lead teams in India, China and Taiwan to fix bugs and implement sub-features.

Architect, Magma Design Automation.(acquired by Synopsys), Apr 2007–Feb 2012

The sole author for Titan Auto-AVP product.

•Start from scratch to accomplish a new custom placement platform for Magma. Overcame major deficiencies by competitors. It supports complex analog design issues comprising of millions of devices with concurrent constraints, design rules with different sizes of rectilinear, standard blocks, multi-height standard cells, leaf-level devices, CMOS or I/O pins each having different uneven gridding, spacing, orientation and abutment rules. Invented interactive Constraint-aware editing protocol/core to tightly work with layout editor through TCL/GUI commands/callbacks.

•Invented new force-driven/hierarchical sequence pair packing with numerical constrained algorithms, machine learning techniques and Poisson equations to optimize connectivity and resolve timing/DRC issues with topological constraints and incremental placement simultaneously. Developed in hundreds of thousand lines of C/C++/Tcl/Tk code on Linux.

•Lead different teams in China/India to implement sub-features and integrate the tool onto different platforms through 10+ releases.

Architect, Cadence Design Systems, Inc., Aug 1997 – Apr 2007

Senior Software Engineer, (Cooper & Chyan Technology, acquired by Cadence),

May 1995 - Aug 1997

The sole author for Virtuoso Custom Placer placement engine.

•Authored the architecture from scratch, created and maintained the entire design flow, roadmaps, specifications, interfaces and algorithms for Cadence’s next generation constraint/congestion-driven all-purpose device-level placement tool in hundreds of thousands lines of C/C++/Skill code. Beat 5 internal products and become the custom placer for Cadence. Invented database-independent APIs and used state-of-art clustering, quadratic optimization, annealing, compaction algorithms to produce industry-leading results both in quality and speed. The tool places mixed standard cells, I/Os, devices, analog, datapaths and blocks simultaneously all in one single engine; still sold by Cadence after left for 12 years.

•Lead a 7-people’s team to integrate the engine directly into the Virtuoso/DFII/OpenAccess product environment through C++ APIs.

•Responsible for all architectural issues involving device-level automatic floorplanning, user interfaces, flows, database I/Os, PCR management and regression tests.

Senior R&D Engineer, Synopsys, Inc. Oct 1992 – May 1995

Initiated the first Synopsys physical floorplanning/placement tool,

•Brought Synopsys into the physical design world by creating a global placer in synthesis environment using GORDIAN to improve the predictability for synthesis tools. (predecessor of Synopsys ICC placement product)

•Co-designed the architecture of a hierarchical physical view manager, wrote interfacing modules between design compiler, prime-time and physical core data to efficiently handle the data transformation between logic synthesis and physical design tools.

Senior Member of Technical Staff, ArcSys inc, (acquired by Synopsys through Avant!)

•Authored the first fixed die detailed routing tool for the startup, an area-based dynamic/incremental DRC checking system in ArcGate, which ran 100x faster than the traditional DRC/LVS checking. Invented dynamic rip-and-reroute, window-based algorithms to handle routing forests, track connectivity information and improve routing patterns in the most efficient ways.

•Developed numerous placement utilities, interfacing and gate array tile-matching modules for the ArcGate placer product. Part of the technologies lead into Avant! IPO and Syopsys acquisition.

R&D Engineer, LSI Logic Corp. Sep 1990 – Oct 1992

One of the innovators in the LSI CAD development team.

•Obtained a patent for a Metal Utilization package to solve lonely wire problem in DFM.

•Developed various utilities for IC layout designers, like boundary scan ring placement, placement legalizer, rectilinear hierarchical functional shape editing for top-level floorplans. (LSI patent)

•Support and help layout designers to use CMDE tools correctly and efficiently.

Education:

Master of Science, Computer Engineering, Syracuse University,

Member of Tau-Beta-Pi, honor society for international students.

Major Projects:

Using perfect shuffle to solve FFT on an SIMD machine; Automatic PLA synthesis/folding/routing system using YACC/simulated annealing & Mentor GDT tool; Automated laryngeal recognition system; SECD matching architecture designs/simulations.

Bachelor of Science, Computer Engineering, National Chiao-Tung University, Hsin-Chu, Taiwan,

Set department record for credits obtained in 4 years with high honors.

Major Projects:

Micro-processor-controlled large scaled Chinese LED display board; Personnel database management system; Logistic and transaction control system for small corporations; Pseudo stack machine assembler and emulator.

Patents:

Patent Number

Title Of Patent

Date Issued

5818729

Method and system for placing cells using quadratic placement and a spanning tree model

October 6, 1998

5654897

Method and structure for improving patterning design for processing

August 5, 1997

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