Layout Engineer Senior Staff
Resume:
Tae Soo Chun
Experienced Layout Engineer
San Diego, CA 92128
**********@*****.***
OBJECTIVE
Analog Mixed-Signal Layout Engineer position
EXPERIENCE
Qualcomm, San Diego, CA — Senior Staff Layout Engineer December 2017 - July 2023
Led team of layout engineers on multiple SERDES projects.
● Delivered 3nm/4nm FinFET(TSMC) SERDES layouts.
● Delivered BTO/MTO on time.
● Provided and updated estimates for required resource allocations.
● Assigned tasks to individual team members according to skills and capacity.
● Communicated and collaborated closely with circuit designers. Followed up on engineer change orders (ECO).
● Responded to process development (PD) requests and provided fixes to address EM/IR drop issue, UBM density errors.
● Verified top cell (LVS/DRC/ERC/Softcheck/Antenna/CCC/CNOD checker).
● Generated FEOL/BEOL dummy fill and updated LEF/GDS files. Qualcomm, San Diego, CA — Contractor
March 2015 - December 2017
Engineered various DDRPHY layouts as individual contributor.
● Delivered 4nm/5nm/7nm/8nm FinFET(TSMC) DDRPHY layouts.
● Delivered 5nm/7nm FinFET CSI/DSI block layouts.
EveRam Technology, Pleasanton, CA — Contractor
April 2014 - September 2014
Engineered 30 nm Low Power DDR2/DDR3 DRAM Analog block layouts. Suvolta Inc., Los Gatos, CA — Staff Layout Engineer April 2011 - February 2014
Engineered DDC Analog chip layouts.
● Delivered 55 nm/66 nm DDC analog chip layouts.
SKILLS
Extensive industry experience
in custom analog layout with
strong knowledge of deep
sub-micron CMOS process
Solid understanding of LDE,
RC delay, EM/IR drop,
coupling, device matching,
guard rings, shielding, latch
up and antenna effect.
Proficient in interpreting
DRC, ERC and LVS
Strong analytical and
problem-solving skills to
identify and address
layout-related issues.
Cadence Virtuoso XL
Mentor Calibre
LANGUAGES
Fluent in English and Korean
EDUCATION
Sogang University, Seoul Korea — Bachelor of Science, EE
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