Stefan Craciun

352-***-**** — ad4igz@r.postjobfree.com

**** ******* ***., * **** Alto, CA 94303

Professional Skills

Algorithm mapping to digital architecture on FPGA fabric Identifying computational parallelism in applications and accelerating execution times using custom hardware Proficiency in hardware programming languages (Verilog, VHDL) for design development and simulation Board bring-up and hardware debugging

Bare-metal firmware development for real-time applications Hardware analysis, testing and verification using oscilloscopes, logic analyzers, and function generators Work Experience

Deepcell Bio — Menlo Park, CA

Staff FPGA Firmware Engineer May 2021 – Present

Selected an FPGA based frame grabber card and integrated it with a high-speed camera and a host PC

• 10k fps continuous image stream with no dropped frames Implemented the camera sensor correction of raw pixel images

• Flat field correction & image normalization

Designed a foreground object detection algorithm

• Running average background model

Selected and integrated an FPGA dev. board for real-time control of peripheral devices

• Real time cell sorting

Johnson & Johnson Robotics & Digital Solutions (Auris Health) — Redwood City, CA Senior FPGA Engineer June 2019 – May 2021

Collaborated with Enclustra GmbH to configure and integrate a Universal Drive Controller FPGA IP core

• Optimized a BLDC motor driver for parallel commutation of 7 motors on a Zynq 7-series device

• Tuned the control loops to achieve optimal torque and minimize power losses

• Implemented a real-time data monitoring system for performance tracking Collaborated with Beckhoff GmbH to configure and integrate an EtherCAT Slave Controller FPGA IP core

• Created a demo application on the ZC702 and AC701 Xilinx development boards

• Purchased the EtherCAT FPGA core and integrated it on a custom PCB Transferred the FPGA design from a Zynq 7-series SoC to an Artix 7-series FPGA

• Substituted the Zynq ARM core processor with a softcore MicroBlaze to reduce power consumption

• Configured and integrated the MicroBlaze softcore processor as a master processor

• Added DDR3L SDRAM interface for bare-metal execution on off-chip memory Designed sensor integrity & safety checks

• Hall-to-encoder and encoder-to-Hall sensor integrity checks

• Encoder quadrature check

• Motor open-phase and short-phase detection

Designed custom peripheral interfaces optimized for streaming applications

• SSI • SPI • I2C • UART

Designed FPGA binary files for golden and update images used in firmware updates Vave Health — Santa Clara, CA

Senior Hardware Developer February 2016 – June 2019 Developed custom peripheral interfaces for off-chip communication Integrated DSP IP blocks while maintaining timing and resource constraints for overall design Implemented data-flow and communication protocols between Zynq proc.(PS) and FPGA fabric(PL) Exported hardware definition files to PetaLinux environment and generated boot images Defined project requirements and selected electronic components to meet design specifications Designed test benches for functional simulation and completed documents used for FDA clearance submission Hardware Developer September 2015 – February 2016

Xilinx IP configuration & top-level integration

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• AXI-DMA&-GPIO data transfer • Async. FIFO • Distributed&Block RAM • FIR Compiler • CORDIC

• Clock Networks • Serializer/Deserializer ISERDES • IDELAY • FFT/IFFT • Floating Point Operators Board bring-up in Bare-Metal environment using Eclipse-based Vivado SDK SoC ARM-&-FPGA peripherals configuration and real-time verification: • I2C • SPI • UART Designed high-speed, multi-channel data deserialization architecture and interfaced with TI AFE58XX Constructed fully-pipelined 32-to-8 bit image-compression IPs with adjustable contrast and dynamic range Integrated beamforming IPs for B/M-mode ultrasound imaging on Xilinx 7-series SoCs SoCcentric Consulting — Sunnyvale, CA

FPGA Engineering Consultant November 2017 – November 2019 Digital architecture development from software baseline to optimized RTL code Developed and integrated peripheral interfaces for FPGA-to-CPU/sensor data communication

• Multi-channel Direct Memory Access • SPI • I2C

Verified, synthesized and benchmarked RTL IPs to meet design specification Performed hardware bring-up on custom or development SoC boards with real-time Bare-Metal testing AventuSoft — Boca Raton, FL

Embedded Hardware Engineer April 2015 – September 2015 Sensor prototyping and testing: • accelerometers • gyroscopes • pressure & temperature sensors Optimized bluetooth low-energy data communication on TI CC2650DK development kit University of Florida — Gainesville, FL

Graduate Research Assistant February 2011 – March 2015 Center for High-Performance Reconfigurable Computing: CHREC Designed low-latency architectures for accelerating image-processing algorithms on FPGA platforms

• Edge Detection • Feature Extraction & Description • Image Segmentation • Object Classification Computational Neuro-Engineering Lab: CNEL

Mapped Information-Theoretic Learning Algorithms to fixed-point architectures

• Adaptive Filters • Data Clustering • Neural Networks • Correlation & Entropy Metrics Education

Ph.D. – Electrical and Computer Engineering University of Florida: Sep. 2015 FPGA architectures for real-time information extraction and feature-based classification in image processing Master of Science – Electrical and Computer Engineering University of Florida: May. 2009 Bachelor of Science – Electrical Engineering University of Florida: Dec. 2006 Important Publications and Patents

Stefan Craciun, R. Kirchgessner, A. D. George, H. Lam, J. C. Principe, “A Real-Time Power-Efficient Ar- chitecture for Mean-Shift Segmentation,” in Springer Journal of Real-Time Image Processing (JRTIP), Oct. 2014, DOI 10.1007/s11554-014-0459-1

Stefan Craciun, David Cheney, Karl Gugel, Justin C. Sanchez, Jose C. Principe, “Wireless Transmission of Neural Signals using Entropy and Mutual Information Compression,” in IEEE Transactions on Neural Sys- tems and Rehabilitation Engineering (TNSRE): a publication of the IEEE Engineering in Medicine and Biol- ogy Society. Feb. 2011, Issue 19(1) Page(s): 35-44 Stefan Craciun, Gongyu Wang, A.D. George, H. Lam, J.C. Principe, “A scalable RC architecture for mean- shift clustering,” in Application-Specific Systems, Architectures and Processors (ASAP), 2013 IEEE 24th In- ternational Conference on, 5-7 June 2013, Page(s)370-374 Stefan Craciun, Austin J. Brockmeier, Alan D. George, Herman Lam, Jose C. Principe, “An Information- Theoretic Approach to Motor Action Decoding with a Reconfigurable Parallel Architecture,” in Engineering in Medicine and Biology Society (EMBC), 2011 Annual International Conference of the IEEE, Aug. 30th - Sept. 3rd 2011, Page(s): 4621–4624

Stefan Craciun, Alan D. George, Herman Lam, Jose C. Principe, “A Parallel Hardware Architecture for Information- Theoretic Adaptive Filtering,” in High-Performance Reconfigurable Computing Technology and Applications

(HPRCTA), 2010 Fourth International Workshop, Nov. 14th 2010, Page(s): 1-10 2

Patent ref. UF-13401 entitled “PICO: Portable Interface for Cognitive Output.” Patent Application Serial No.61/444,314

Patent ref. Number 51176-702.201 entitled “Dynamic Range Compression of Ultrasound Images.” Application number: 15/470,793

Programming Languages and Tools

VHDL/Verilog; TCL scripting; C; Xilinx-Vivado-SDK; Intel-Quartus; Modelsim; Matlab/ Simulink/System Generator

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