PADMAPRIYA PATIL

+1-361-***-**** ad3z2u@r.postjobfree.com https://www.linkedin.com/in/padmapriya-patil-217b1810a CAREER SUMMARY

Self-motivated Electrical Engineering graduate with experience in LTE, 5G NR SUB6 carrier – add and activation, Network certification, lab experience with Anritsu, KeySight, TBS, 5G, LTE, CDMA, and Network layers, AIR Interface and RAN architecture, analog integrated circuits, VLSI and RF design.

TECHNICAL SKILLS

Scripting/Programming languages: C, C++, Python, MATLAB. Spice simulation tools: LTspice, Hspice. Hardware Description languages: Verilog, VHDL. Tools: Cadence Virtuoso, Cadence, Microwind, Magic, ModelSim, USM, Tableau, Power BI, JIRA Knowledge in: 5G, LTE, RAN, CDMA, Analog integrated circuits, logic design, SoC, RF design, VLSI, and fundamentals of semiconductors. EXPERIENCE

JUNIOR 5G 4G RAN SOLUTIONS ENGINEER ADI WorldLink LLC - Plano Texas Nov 2021 – Jan 2024

• Experienced as Samsung Tier-3 RAN SME, provided support to the RF team in optimizing sites with degraded KPIs.

• As a Tier-3 SME, analyzed, and optimized the failing KPIs on PCC and conditionally accepted sites, post-acceptance, and YOY sites to achieve KPI values at the sub-market acceptance level and improved site performance.

• Extensively worked to optimize and improve KPIs such as RTP GAP, SIP DC, ERAB Drop, DL and UL Tput, RRC SF, RLC Vol, etc.

• Investigated any issues causing a discrepancy against the KPIs that impact the site acceptance/submarket acceptance, both for Trouble Tickets opened by the Contractor, and Trouble Tickets referred to the Contractor.

• Optimization steps involved physical layer, Handover analysis, Power parameter analysis, mobility parameter analysis (A1, A2, A3, and A5), RSSI imbalance analysis, coverage and traffic analysis, priorities, load balancing, timers, individual offsets, antennas, and any other related RF parameter analysis.

• Performed hands-on analysis of performance issues revealed by the KPI discrepancies (i.e., air interface, call processing, etc.) using gNB/eNB logs, XLPT and USM reports, RF checklists, and recommended solutions to meet network optimization expectations.

• Proposed and implemented parameter changes to improve system performance and drive technical solutions to customers through complex organizational dynamics.

• Worked with the RF Engineering and Operations Teams on the cell site’s antenna and RF equipment configuration and database parameters. SOFTWARE ENGINEER RJT Compuquest DBA Apolis – San Diego California Jun 2021 - Oct 2021

• Worked in the lab with live wires, Test Base Station, Anritsu, and KeySight,

• Monitored SA and NSA test cases using the automation tool Axiom with MTFpy framework.

• Analyzed logs using QXDM, and QCAT.

• Debugged set-up-based failures in the lab.

• Worked with tools like QUTS, ALPACA, MTFpy, Axiom

• Worked with iPRT and non – iPRT test base stations. SQA ANALYST BTI Solutions Inc - Overland Park Kansas Feb 2021 – Jun 2021

• Performed E911 Volte and RTT call tests on various Samsung Sprint/Dish devices.

• Performed Rah Regulatory Test cases.

• Performed Anti-fraud and Sprint Mobile Framework test cases.

• Performed wireless data test cases.

• Performed various E911 test cases using the lab.

• Collected logs using the QXDM tool. Analyzed the logs using Wireshark. NETWORK ENGINEER Next Technology Solutions LLC – Dallas Texas Nov 2019 – Dec 2020

• Performed pre- and post-checks on 5G SUB6 sites.

• Performed Carried Add on 5G nodes.

• Executed activation scripts on live LTE sites.

• Checked, blocked, and deblocked emergency (911) Calls on LTE nodes.

• Performed 5G activation procedures for standalone and non-standalone sites.

• Trained in 5G integration procedure.

• Performed 5G carrier – add procedures.

• Performed RET migration for 4478 B5 Radios.

• Performed 8CC mmWave Carrier Add and Activation.

• Performed Retest on Tiger Team SUB6 Activation sites.

• Performed Audits on AdHoc sites.

• Performed Integration and Activation on Mixed-Mode Base Band (MMBB) sites. ACADEMIC PROJECTS

Graduate Research Thesis - Design of Impedance Matching Transformer to Integrate an Antenna on Chip. Jan 2018 – May 2019 A research in analog integrated circuits, RF design, and SoC. The work involved designing an impedance-matching transformer to match the impedances of Voltage Controlled Oscillator (VCO) with a control voltage of 1.2V at 10.55GHz and an antenna on-chip. The results were as follows:

• Calculated the output impedance of VCO using simulating tools: LTspice and Microwind.

• Observed the output voltage and frequency values for loads of 50Ω, 75Ω, and 100Ω.

• Implemented a common drain configuration as a potential impedance matching transformer in cascade with VCO with a nmos size of 130nm. The nmos worked for a high frequency of 10.55GHz in VCO. The layout of the configuration was drawn using Microwind.

• The common drain configuration did not prove to be good as it was an ideal common drain, but it did help in circuit isolation.

• Suggested common drain using BiCMOS in CD-CC configuration for future work as gm (BJT)>gm (MOSFET) can potentially reduce the output impedance of the VCO as it provides lower output impedance as compared to common drain configuration. Design and verification of Voltage Controlled Oscillator (VCO) for RF devices. (LTspice, Microwind, RF design Spring 2018

• Considered a test VCO from the research work by Sairam Singh et al. which consisted of five inverter stages forming a current mirror, a nmos and pmos attached to the first stage, and another inverter as a buffer at the last stage.

• Created and simulated the layout using simulation tool Microwind and obtained frequency up to 10.55GHz at control V= 1.2 V, voltage V = 1.2V.

• Observed the change in frequency of operation with a change in control voltage.

• Derived the spice netlist and simulated using LTspice and verified frequency and power for control voltage of 1.2V.

• The VCO worked for high frequencies up to 10.55GHz at a control voltage of 1.2V. Design and simulation of the layout of an ideal common drain configuration. (LTspice, Hspice, Microwind) Fall 2017 Considered an ideal common drain configuration to demonstrate its character of high input impedance and low output impedance. Implemented a nmos of size 130nm and initial load resistance of 50Ω.

• Wrote spice netlist for common drain configuration and simulated the netlist on LTspice and Hspice.

• Created the layout and simulated the common drain configuration in Microwind.

• The circuit generated high input impedance and low output impedance.

• Design and Verification of ring oscillator. (LTspice, Magic) Fall 2016.

• Wrote spice netlist for a 3-stage ring oscillator.

• Simulated the netlist using LTspice.

• Generated layout of the oscillator using Magic; a simulation tool. Calculated time delay and the frequency of oscillation using =1/2 EDUCATION

Master of Science in Electrical Engineering. Texas A&M University, Kingsville, Texas. GPA: 3.7/4.0 May 2019 Majors: VLSI, Analog Integrated circuits, Fundamentals of Semiconductors. Bachelor of Engineering in Electronics and Communication Engineering B.I.E.T. Davangere, India. GPA: 3.0/4.0 June 2015 Majors: VLSI, Microprocessors, Digital Signal processing.

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