Angela Toulouze Melouani

***** ******

Laguna Hills, CA 92653

949-***-****

ad3upq@r.postjobfree.com

Fluent in French, English & Arabic

CAREER SUMMARY

Experienced Analog/Mixed-Signal IC Layout Engineer with experience in the follow process technologies: TSMC 90nm 6-layer metal CMOS/RF CMOS and 0.1um 5-layer metal BICMOS Nwell technology

Computer skills include Cadence and Mentor Graphics design tools and verification tools, such as Caliber, Assura and Cadence Dracula

Comprehensive layout design skills in analog device matching, minimization of parasitic layout elements, electromigration and ESD/Latchup immunity

PROFESSIONAL EXPERIENCE

July 2019 – Present Spectra7 Microchip Corporation

IC Layout Designer (Consultant)

Providing layout for TowerJazz SBC18h5 and SBC18h3 process with seven (7) metals

Performed layout for oscillator/polybias/master bias/test mux/fuse switch/PtatBias/POR and POR comparator/bandgap, and deferent regulators (3.3v/2.8v/1.8v) and a level-shifter

Assisted the layout team in routing the connections between core blocks to the level-shifter to the I2C block, using Cadence VXL for layout activities on IC6.1 OA and PVS for backend verification (LVS/DRC/ERC/ANT)

June 2015 – Present RDGZ Consulting Inc.

Mask Layout Designer (Consultant)

Provided consulting work for Microchip and Tensorcom Inc.

Provided layout for IBM 28nm and 40nm Global Foundries

Performed sub-bock level layout for a Bluetooth chip, using Cadence VXL for layout activities on IC6.1 OA and Calibre for backend verification

Nov 2014 – Dec 2014 Himax Imaging

Mask Layout Designer (Consultant)

Provided layout for TSMC 90nm technologies, CIS (CMOS Image Sensor) process, 4-metal

Worked on sub-blocks using Cadence VXL/Laker Custom Design Tools for layout activities on IC6.1 OA, and Assura for backend verification

Jan 2013 – March 2014 Spectra7 Microchip Corporation

Mask Layout Designer (Consultant)

Mask layout contractor providing layout for 28nm LN28LPP process technologies

Laid out a Tx driver, bias circuits, ADC and DAC blocks

Used Cadence VL and VXL for layout activities on IC6.1 OA, and Calibre/PVS for backend verification

July 2012 – April 2013 Monolithic Solutions

Mask Layout Designer (Consultant)

Jan 2013 – April 2013

Worked on TSMC technology nodes: 65nm LP MSRF 1.2/3.3v 6-metal; used new Cadence version OA IC6.1

oAdditionally understood PVS verification tools LVS/DRC

July 2012 – Aug 2012

Provided layout for 40nm TSMC RF CMOS 8-metal layer process technologies for flip chip Wi-Fi and Bluetooth, with DNW

Laid out standard cells, a crystal oscillator, bias circuits, CML2CMOS and opamp circuits

April 2012 – Dec 2012

Acquired strong knowledge of transistor, schematic, logic and complex logic fundamental

Understood various device cross-sectional views and major fabrication steps

Understood clock delay/skew issue and clock routing requirement

Understood resistance, capacitance, inductance and the associated RLC parasitic technique used to reduce IR drop, EM and antenna issues

Applied device matching and noise reduction technique in analog circuit layouts

Acquired knowledge of chip floor planning: cell/block and I/O placement, power bus routings

Designed various circuit blocks with 0.1um, 5-layer metal BICMOS nwell technology, including all basic and complex logic, data latch, D flip flap, shift register, SRAM, bias, PLL, clock generator, ESDs, I/O devices and bond pads

Final project was a BiCMOS mixed-signal transceiver circuit

EDUCATION & OTHER TRAINING

Coursework, Silicon Drafting Institute, San Jose, CA

oAdvanced BiCMOS IC Mask Layout Designer Course, April 2012 – Dec 2012

oCadence Virtuoso Layout Editor (VLE), Virtuoso XL Editor (VXL)

oLayout Design Training Course

BA, Arts, Mohammed V University, Rabat, Morocco, 2004

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