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Louis Jacob email *: ad3s11@r.postjobfree.com

email 2: ad3s11@r.postjobfree.com

Electrical Engineer

Laval, Qc, H7H 2Y3

514-***-****

Education

B.Sc. in Electrical Engineering UNIVERSITE LAVAL, St-Foy (Quebec) General Profile

Passionate and self-motivated Hardware board designer and FPGA/CPLD designer in the following fields: medical, telecom, flight simulators, security systems, printers/scanners. Expert in the design of high speed and high density/complex boards (designed PCBs of up to 24 layers, using BGA parts with over 600 pins). Applies proven design methods to create electronic boards. This includes the engineering specification, schematic entry, simulation, worst case analysis, followed by thorough PCB layout guidelines (critical component placement, stack up, terminations, clock trees, controlled impedances, trace to trace spacing, etc…). I typically work with the PCB designer during PCB routing phase of the design to verify the trace routing as we move along. Designed multi-processor boards using DDR2/SDRAM, SRAM, Flash, 3Gigabits/sec SERDES, high pin count CPUs such as the MPC755/MPC107, IBM PPC405, MPC860T, TS-201 DSP, IXP2350, Wireless Pro5116, TMS320C30, 80186, 6809, etc... Also, designed using smaller CPUs/DSP such as, ADSP21mod870, STM32F765, 87C51, MSP430, PICs18F, etc... Designed systems with PCI 66MHZ/64bit, H110 Telecom bus, SCSI bus, Ethernet, I2C bus, SPI bus, CAN bus, MDIO bus. Careful with the implementation of clocking trees, terminations, and signal timings. JTAG implementation and remote firmware updates of programmable devices. Familiar with Rj+Dj jitter analysis and clock wander issues.

Currently looking into implementing DDR4 and PCIe technologies for a future design. Proficient in VHDL programming of FPGAs and CPLDs such as Xilinx, Altera, Lattice, Actel etc. (Also used the ‘ABEL’ programming language and some knowledge of Verilog). Good experience creating state numerous machines, dual clock domain FIFOs, camera control, PCI arbitrator, DSP and CPU memory interfaces, serial bus interfaces, I/O registers, etc.. Knowledgeable in ‘C’, Pascal, Basic and assembly language. (Some knowledge of Labview). Also developed a strong expertise creating linear analog circuits using opamps while paying special attention to their key specifications such as Gain-Bandwidth Product, current vs voltage feedback type, input bias/offset currents, offset voltage etc... Careful with gain & phase margin for feedback loops. Designed linear and switching regulators, feedback loops (AGC), several ADC and DAC circuits, audio and video amplifiers, over current protections, current sensing, thermocouple monitors (uV range), battery chargers, Lossless power ‘ORing’, etc… Careful with the power dissipation to prevent excessive heating of the components.

Lots of experience in lab troubleshooting, using oscilloscopes, logic analyzers, network and spectrum analyzers, DVM, thermal imaging etc.…

Very knowledgeable with multiple CAD tools such as Mentor Graphics suite (Viewlogic/Xpedition/IO designer/Pads) and Cadence’s (Orcad / Allegro/ Composer). Simulation softwares: Modelsim for VHDL/FPGAs, Hyperlynx for high-speed designs, MultiSim and LT Spice for analog designs. Some knowledge of MathCAD and Minitab. 2

Work Experience

February 2010 to Jan 2024 (14 years)

Principal Electrical Engineer, Medtronic-Cryocath LP (Medical Industry)

• Design of a new Patient Board for the next generation of Medtronic Cryo Ablation console (Nitron Console). Based on an STM32F765 CPU. Functions include 3 x thermocouple (TC) channels with dual monitoring mechanisms (one precision analog amplifier into 12 Bit ADC + one direct non-amplified 24- bit sigma-delta ADC), a programmable tri-frequency leak detection system, programmable analog bandpass filters and optical detector. TC monitoring accuracy is better than +/- 2 C without software calibration and +/- 0.2 C with calibration. Uses CAN/I2C/SPI/RS-232 digital communication interfaces. Patent is pending.

• Designed a 12-channel thermocouple (TC) data acquisition board. Contains ADCs, diff amps, CPU, FPGA. Used for the Pulse Field Ablation project (PFA). Monitors TC voltage in the micro volts (uV) range while operating in a very high voltage application (~ 2kV). Performed the detailed design specific, noise, settling time analysis and simulations. Patent is pending.

• Developed an Automated Test System to validate the production of the pressure & optical sensor boards assembled in the AF Cryo catheters. Designed the wrote the Labview code.

• Created a programming a hardware box used by Medtronic production to program catheters (over 200,000 units /year).

• Redesign of several electronic boards (totally or partially) used in the Medtronic CryoConsole and Artic Front catheters. (analog /digital/FPGA work).

•Created several engineering reports describing in details the existing circuit performances and their limitations (‘Worst case’ analysis).

• Initiated the effort for the detailed electrical characterization of cryo-catheters model.

• Support to manufacturing and field engineers.

August 2008 to Feb2010

Hardware Engineer, Exeo Systems (Remote security systems)

• Digital and analog design of multiple modules, including Digital section of a wireless dimmer, camera scanning interface, capacitive sensing switches, power supply section integrating a battery backup using an ideal ‘Oring’ scheme (near 0 loss) and an intelligent power sequencer, RFID reader with low EMI pollution. Wrote the FPGA code (VHDL) for the camera interface. Wrote the ‘C’ code for the power sequencer. Redesign of a smoke detector module in order to increase battery backup operation from a few days to several months while maintaining the original functionality. Sensitive to power consumption reduction in the design of battery operated devices (low power modes, leakage currents, conversion losses etc…). Created the detailed design specs describing my designs.

June 2007 to July 2008

Hardware Engineer, IPC Positron911, Montreal (Telecom industry) Involved in the technological transfer and re-design of a TDM system (switch, MPC870 based) from IPC- Orbacom(New Jersey) to IPC-Positron (Montreal).Also provided Engineering Support to the software team.

Oct 2002 to June2007 and March 1998-Oct 2000 (7 years) Hardware designer, SR Telecom, Montreal, (Point to multipoint TDMA and CMDA)

• Design of a three sector Wimax phy modem based on the Analog Device Tiger Sharc TS-201 DSP(600Mhz, BGA 676 pins). This design includes 3 x ADI TS201 DSPs +3 x Virtex4 FPGAs, a PCI to DSP bridge, onboard SDRAM and Flash, a Quad Serdes and 6 Fiber Xcvers. This 20 layer board is part of the standalone Wimax Base Station system. Wrote the VHDL code for the CPLDs and part of the FPGAs code.

• Design of a single sector Wimax phy modem based on the Analog Device Tiger SharcTS-201

(600Mhz) DSP. Includes a 64 bit, 66mhz PCI to DSP Bridge, a Virtex 4 FPGA,128MB of 100MHz 3

SDRAM and 16MB of Flash. Wrote the VHDL code for the FPGA, which includes a 125MHZ DDR interface between the DSP and the FPGA (Link port)..

• Design of dual DDR DIMM memory interfaces (150Mhz) and the power sequencing for a base station board, which uses the Intel IXP2350 cpu(Westport, 900Mhz, BGA ~1752 pins).

• Design of a Wimax (802.16D) Subscriber Station board based on Intel’s WirelessPro5116

(Rosedale) chipset.

• Design of Compact PCI Base Station controller card. MPC860T based, with SDRAM, Dual PCI buses and H110 telephony bus, Hot Swap Compliant. Includes a V34 Digital modem

(ADSP21mod870). The FPGA logic executes several tasks: Manages board redundancy

(Active/Standby), H110 clock mastering/monitoring/Bit Error testing logic (BERT). The FPGA also performs PCI arbitration (Rotating Priority). Clock Mastering provides Stratum 3 Level synchronization (normal/holdover/free-run modes). The FPGA and FLASH devices are remotely re-configurable. The card also has an Ethernet (10 base T), an RS232 ports, dual HDLC, dual I2C buses, quad IOM2 channels and a battery backup real time clock. Wrote the VHDL code for the FPGA and 2 CPLD’s (XC9572XL) used on the BSC card.

• Design of a Service Module card to be used the compact PCI shelf. Based on a PIC16C73 micro-controller. Provides triple Line Interface Units (LIUs for E1/T1 lines), I/O alarms, temperature and battery (-48V) monitoring circuits. Wrote the hardware design specs and test plans for the above designs. Produced a set of PCB simulations, stackups, guidelines and placement. Supervised the PCB routing. Worked on the lab design validation and provided support to production. Programmed some test software for the BSC card and the Wimax phys.

• Worked on the completion of a CDMA system. This system was purchased by SRT from another company (Nera) and required some modifications. My duties included supervising the changes to the Base station side (6 cards) to solve problems such as jitter immunity on the T1 recovered clock, cost reduction and obsolete parts replacement. My redesign work included: clock synchronization to make it jitter compliant to the AT&T62411 spec and also Stratum 3 compliant, upgrade from EDO to SDRAM and the elimination of an expensive off the shelf module by integrating alarms onto one of the boards. Lab tested the re-designed cards. Produced test plans and provided hardware support to software and production. Oct 2000- Sept 2002

Hardware designer, Hyperchip, Montreal, (Telecom, High Speed Core routers)

• Lead designer on a Shelf controller card (Team effort of 4 engineers). The card dimensions =~ 17 x 15 inches with 18 layers stack up. The CPU core was based on an MPC755/MPC107 chipset and included external L2 cache, 1 GByte registered SDRAM (DIMM modules), (buffered) Flash Memory, Dual PCI buses, Ethernet and RS232 ports and 2 CPLDs. The back end was comprised multiple FPGAs and ASICs. I personally designed the SDRAM / Flash and PCI sections and wrote the VHDL code for the 2 CPLDs.

• Design of an Optical Interconnect module (OIM). This is 3.125 Gb/s board. Its purpose is to pass traffic between boards in the same shelf (electrical path) and also between shelves (optical links). The board dimensions =~ 15 x 9 inches with a 20 layer stack up and chips fully populated on both sides. The CPU core was built around an IBM PPC405 chip with SDRAM and Flash, Ethernet and RS232 and a fairly large CPLD (for which I wrote the VHDL code). The rest of the hardware was made of several SERDES, Xpoint switches, VCSELs (lasers) and PIN receivers. On both designs I worked closely with the Signal integrity group to validate IBIS models and routing topologies. Provided a placement and a list of guidelines to be followed by the PCB designer. Supervised the PCB layout. On the OIM, I also did some jitter budget (Random + Deterministic) on the 3Gb/s data paths to achieve 10E-12 or better BER. July 1997 to March 1998

Hardware & software designer, Novimage (Widecom), Montreal, (Wide format scanners & plotters industry)

• Design of a SCSI (‘Scuzzy’) interface card. Provides a fast PC interface to Wide format scanners and plotters. Based on Adaptec`s AIC33C96 ESBC chip. The FPGA logic supports multiple resolutions, for both B&W and Colour formats. FIFO memories (controlled by the FPGA) throttle the data transfers.

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• Wrote the VHDL code for the FPGA. Also wrote the application firmware for the scanners (6809 assembly language) and programmed the AIC33C96 SCSI chip in its proprietary language. May 1992 to July 1997

Hardware designer, CAE ELECTRONICS, Montreal, (Flight Simulators industry) Created multiple designs including:

•Video Timing Generator. Synchronizes and genlocks multiple raster signals. Blends stroke with raster video sources. Supports NTSC and PAL formats. Provides a programmable position of the stroke source within the raster picture. Implemented a custom sync extractor for fast detection of the Hsync and Vsync from the raster source. Wrote the programmable logic code for the 2 CPLDS on the card.

•Analog Color Video Processor card. Supports NTSC and PAL formats. Inputs 12 RGB video signals and generates 3 RGB outputs. Superimposes (sums) 3 RGB pairs to give the 3 RGB outputs onto which pixel switching with another source is done. Design of the AGC control loop to compensate for signal amplitude attenuation. Wrote the ABEL code for the CPLD on the card.

•I/O Matrix Controller card. Efficient and cost saving solution which interleaves activation and monitoring of up to 1024 points when configured as a 32 x 32 matrix. Wrote the ABEL code to implement the numerous state machine controls in an FPGA.

•Simulated Instrument LCD controller. Based on an 87C51 uCon and multiple LCD drivers. Oct 2023

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