Truong Hoang

*** ********* *****, *** **** *****

669-***-****

ad33ld@r.postjobfree.com

Seeking for ASIC/SOC Design

Management

QUALIFICATION

Qualification: Lead all phases of Project Management, Plan and Manage project from PRD/MRD till production, Align business goal and technology solutions. Experience in Team Building and Leadership. Project Life Cycle Management. Project Budgeting Monitor. Years experienced in HW/SW/IP Program Management, Managing Third Party Hardware and IP suppliers, chip level manufacturing and external Design Services. Years in Circuit Design, ASIC Design, IP/Chip Integration, system-level bring-up. Expert in Low Power Design as part of working at Baidu/Qualcomm/Broadcom and STM. Build experience in car sensor experience,

● Build relationship with Internal cross-functional team, and Third Party vendors, customers.

● Manage Lidar and Cameras Unit, mechanical tests, EMI, and production release planning.

● Image Processor and Vision Processor Unit Program management on FPGA and SW enablement.

● Artificial Intelligence System on Chip architect of Autonomous Product Design, target performance, IP selection, IP integration, VPU chip architect and working with external CNN IP team.

● Experienced in both HW and SW program management. Have experienced with Confluence/Jira/Salesforce for management software.

● Mitigate risks factor by analysis of the financial and statistical data. Anticipated and manage change quickly on a rapidly growing project.

● Certified Semiconductor Functional Safety Based on ISO 26262 (ADAS)

● Certified Functional Safety ISO 26262.

● Interface with Foundry Manufacture and IP vendors for IP Qualification, Specification and Schedule. Focal point for contact between Analog, PDK enablement between IP vendors, customer engagement and foundry.

● Project management team member across locations (Shanghai/Bangalore), cross training and cross execution among team in different working time-zone.

● Deep understanding of SOC Design in advanced IC process nodes, 7nm/5nm process enablement, tradeoff between Power Area and Cost. PDK enablement for advanced process node, enablement for Analog Device, ESD design guidelines, decomp of FEOL and BEOL, physical design rules etc

…

PROFESSIONAL EXPERIENCE:

Mediatek Inc, Santa Clara, CA, May 2022 - now:.

Deputy Director of Program Management

● Manage customer ASIC project from RTL to GDS including Package design, Post silicon to Mass Production.

● Involved in Customer project technical accessment to Project bidding.

● Planning milestone including Synthesis, DFT, Physical Design, package design, vendors management and tracking project status.

● Engaging with IP, IP vendors, IP evaluation, Package OSAT etc …

● Post silicon ATPG, CP and Final test. From system level test to Mass Production etc … Qualcomm (Nuvia Inc acquisition), Santa Clara, CA, May 2020 - May 2022:. SOC Physical Design Director

● Manage Third Party IP, SOC portion of the chip set which involved in DDR5 and CXL.

● Overseeing the DV/Silicon Implementation (DFT/PD/Package design) portion

● Engaging with IP/Parts vendors, 3rd party Suppliers to make sure the deliverables and schedule in line.

● Involved in CPU integration, SOC portion of the dataserver CPU.

● Manage a team of 10 Physical Design engineers implementing CXL/PCIE and DDR5 controller. Baidu, Sunnyvale, CA, August 2018 - June 2020.

ADAS SOC Program Manager..

● Project of Autonomous Self-driving Technology. Participating in SOC architect, collecting requirement and defining what should be included in SOC for the next generation of product based on its functional and performance specs. This resulted in detail Vision Processor and CNN AI engine Specification.

● Oversee the product testing of Lidar and Camera as far as EMI, mechanical test of shock and vibration.

● Engaging with IP/Parts vendors, 3rd party Suppliers and Car customers, benchmark IP, selecting IP, negotiate for IP cost, Lead vendors and customers meeting. Identify potential suppliers and engage working with them on quality and delivery schedule.

● Plan and Track FPGA prototype design and its software release for L3/L4 of Autonomous Self driving Car product.

● Hold regular review with outside vendors to review weekly status and mitigate plans for schedule pull-in.

● Manage and prioritize EDA tool bug and Functional bug with the use of JIRA, PLM.

● Work on floorplan and make sure the floorplan makes sense for data flow and mixed signal noise from one IP to the other if placing them too closed. Architect Low Power strategy of power down blocks.

● Tracking customer system, HW/SW released schedule, issues tracking for each release captured in Jira with assigned owner. In addition, keeping track of supplier delivery with payment schedule.

● Manage ASIC design in FPGA level, tracking the integration with Sensor Engineering Team, Radar Engineering Team and Lidar team.

● Manage interdependencies of multiple group from multiple sites as far as communication and deliveries.

● Working with Lidar/Radar TPM and aligning schedule weekly.

● Conduct daily or weekly meeting using Microsoft Projects and Agile to track schedule and mitigating plans for resource and schedule shortage.

Global Foundries, Santa Clara, CA, August 2016 – August 2017 Senior Technical IP Program Manager

● Tasks include Reviewing and Approving IP SOW (Statement of Work) with Synopsys IP design groups in 7nm and 22FDX process node.

● Managed the entire Product Life Cycle of IP through the JIRA/Agile/Salesforce system. IP in works included Serdes, LPDDR, USB, PCIE, Stdcells and IO, MIPI etc ..

● Define metal stack requirement, ESD spec, PVT corners, financial milestone for delivery which matches with customers demand and schedule.

● Enabling customer with new process technology enablement of 7NM, keep track of testchip tapeout blocks, shuttle date, DRC/DFM waive process. Continue communicate bug fix for new PDK release and layout suggestion.

Qualcomm, San Jose, CA, Jan 2006 – Aug 2016

Director of Physical Design

● Manage Physical Design of WLAN/BT/FM/NFC products including Mobile application, Enterprise Wifi routers.

● Highly integrated system of Serdes/802.11AX/DDR4/PLL. Highly integration of RF/Analog/Baseband all in one SOC.

● Helped out with engineering work in 10LPP and 7NM for Place and Route the GPU block, Place and Route the WLAN blocks with embedded PLL/ADC/DAC/Package bump pushed down, performing IR and ESD check using Apache Redhawk tool.

● Handon in physical design, working with package driven IR drop analysis.

● Make sure the ICC/ICC2 tool is keeping up with the Double Pattern and other advanced requirement from 16ff and 14nm/10nm DRC rule and placement constraint, MxCut, Dcut.

● Familiar with whole CPF/UPF flow front to back. UPF driven layout OR CPF driven floorplan.

● Closed Timing for critical congestion blocks with at speed test, using MMMC timing driving flow. Magma Design Automation, San Jose, CA, Jan 2002 – Dec 2005 Senior Staff Application Engineer

● Support Toshiba, Broadcom customers with adopting Blast Fusion tool by building Physical Design flow from RTL to GDS.

● Benchmark Magma tool against Synopsys ICC and SOC Encounter.

● Train customer in using the tool for taping out product, supporting bug report, working on workarounds.

● Familiar with whole CPF/UPF flow front to back. UPF driven layout OR CPF driven floorplan.

● Help benchmark new product from Magma from Synthesis to Physical Verification tool. Broadcom, San Jose, CA, Jan 1998 – Jan 2002

Senior Physical Design Manager

● Started building the group from 2 into 20+ PD engineers to work on parallel projects delivery on Home Phone Network and Wifi products.

● Work on highly integrated SOC using Ethernet, Wifi, USB, NOC (Sonic Bus), using Physical Compiler from Synopsys and Apollo from Avanti.

● Lead projects from top level, push down floorplan for blocks Physical Design Engineers. Lead Timing signoff team by running Crosstalk Timing analysis, Voltage storm for IR drop.

● Timing closure using Primetime and internal ECO tool.

● Manage CAD team to build timing closure flow from Layout/Celtic for noise/STA design closure loops. STM, San Jose, CA, Jan 1994 – Jan 1998

Designer/Physical Design Lead

● Worked with RTL (VHDL) on the interface control logic, synthesis and using Cell3 layout for Place and Route.

● Support Seagate with their design and simulation.

● Learned FPGA mapping VHDL code into FPGA logic from Cypress. Sun MicroSystems, Mountain View, CA, May 1990 – Jan 1994 Senior Circuit Design Engineers

● Managed Standard and DataPath Cells design for Sparc10, Sparc20 Projects.

● Data Path cells are used for Arithmetic operation such as Multitplier and Divider.

● Manage a circuit design team of two junior VLSI designer. Review Texas Instrument Memories Design used for Sparc projects before it taped out.

GM-Delco Systems Operations, Santa Barbara, CA, May 1985 – April 1990 Senior Circuit Design Engineers

● Design Macro cells, SRAM, CAM

● Data Path cells are used for Arithmetic operation such as Multiplier and Divider.

● Manage Radiation Hardness VLSI library which is required for Military systems.

● Design micro controller using Verilog language.

EDUCATION

U of Utah, Electrical Engineer, Salt Lake City, Utah. Coursework: VLSI, Analog Design, Digital Signal Processig, Microwave, Control System. Finished all requirement.

Haas School of Business School, Berkeley, CA

PMP program

(Not finished yet)

ADDITIONAL SKILLS _

Computer Music composition: Jazz School of Music, Berkeley, CA.

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