Varshini Reddy Medipalli

806-***-****, ad2wib@r.postjobfree.com

SUMMARY

7+ years of experience in Embedded systems, Circuit simulation and design, PCB design.

Good knowledge on EPROM, NOR Flash, Microcontrollers and PLDs.

Familiar with signal integrity, ground bounce, power supply noises.

Good Understanding of Statistical data analysis, Design for Test (DFT) techniques and Six Sigma Standards.

Good Gained technical knowledge in coding and testing of Digital systems and Languages like C, C++, Embedded C, Perl, System Verilog through tools like Keil, Xilinx, LabVIEW, HSpice, Cadence.

Gained good Knowledge in Oscilloscopes, Spectrum analyzers, Vector Network Analyzer, Logic Gates, Multimeters.

EDUCATION

Master of Science in Electrical and Computer Engineering May’ 16

Texas Tech University, Lubbock, Texas GPA-3.75

Bachelor of Technology in Electronics and Telematics Engineering May’ 13

Jawaharlal Nehru Technological University, India GPA- 3.6

CERTIFICATIONS

Engineer-in-Training (EIT) certification by National Council of Examiners for Engineering and Surveying(NCEES).

TECHNICAL SKILLS

Programming Language : C, C++, Java, System Verilog,Verilog, VHDL, Python,Assembly Languages

Design and Simulation Tools : PADS Logic,PADS Layout Cadence, LabVIEW, LTspice,Hspice, MATLAB,

Multisim, Kiel, Xilinx, Questasim,Altium,PSpice

Test Equipment : NI PXI, TI VLCT ATE, NI STS T4, Keithley 2400 SMU, Agilent,

Oscilloscope, Frequency Response Analyzer, Vector Network Analyzer,

TI XDS100v1, v2, v3, Segger J-Link.

Device Drivers : NI DC Power, NI HSDIO, NI MYDAQ.

Statistical Software : JMP, Stat Pad, Savage Testing System.

IDE’s : IAR embedded work bench for ARM microcontrollers, Code Composer

Studio,Code Warrior, Atmel Studio, Silicon Labs:Simplicity

Studio.

EXPERIENCE

[March ’20-Present] Senior Device Engineer at BPM Microsystems, Houston, Texas

-Create schematic, layout for the new product development like socket modules designed for programming Integrated Chips using Mentor Graphics PADS Logic, Altium Designer and PADS Layout.

-Creation of PCB designs considering EMC guidelines and inputs from the project in order to achieve optimized design in terms of timing, cost, quality and manufacturability.

-Test and review PCB designs.

-Conducted detailed circuit analysis, utilizing design tools to identify and resolve performance issues, resulting in improved overall circuit performance and reliability.

-Update BOM (Bill of Materials) for the socket adapters parts and maintain the records.

-Prepare test plans and test reports for quality assurance purpose.

-Build firmware to support the programming of the flash memories of the integrated chip.

-Use Integrated development environments to program devices from manufacturers like STM, Texas Instruments, Analog Devices, Silicon Labs,NXP, Xilinx, Renesas, Intel, Cypress, Freescale Semiconductors Microchip Technology, Spansion, Micron, Macronix etc.

-Use logic analyzers like Saleae, Beagle to debug and decode protocols like SPI, I2C, SMBus, PMBus,Serial, JTAG, SWD, Atmel SWI, DAP, UART, RS232,RS485,LIN etc.

-Work with UART bootloaders.

-Write algorithms for eMMC, NAND device programming.

-Implementing various Bad Block Management and Error Correction Code schemes for raw NAND devices.

-For debugging, we use oscilloscopes, protocol analyzers, voltmeters, breadboards, IAR embedded work bench for ARM microcontrollers Cortex M4F, Segger J-Link, TI XDS100v1, v2, v3, Code Composer Studio, Atmel Studio, Silicon Labs: Simplicity Studio.

[Nov’16-March ‘20 Device Engineer at BPM Microsystems, Houston, Texas

-Write algorithms to support Non-Volatile memory devices, PLD and Microcontrollers, system on chip.

-Create and update Failure Mode and Effect Analysis(FMEA) for designs.

-Design, develop and oversee validation components and work on inspection plans and inspection feature assessment.

-Perform 8D to analyze the root cause of the failure, document the containment action, permanent corrective action after a bug has been resolved.

-Perform DMAIC and DMADV methodologies of six sigma for business transformation.

-Follow the 5-why and fishbone diagrams for seeking out the source of a problem in a service process or a product defect.

[July’16- Nov’16]Associate Engineer at Tech Mahindra Americas INC, Plano, Texas

Designs and develops user interfaces to internet/intranet applications by setting expectations and features priorities throughout development life cycle

[Feb '16 - May '16] XFAB SILICON FOUNDRIES – Intern

Responsible for survey of Commercial SiC Epitaxial growth equipment and Processes

-Investigate and determine if it is economically feasible for X-FAB to grow their own SiC wafers

-Investigate SiC Epitaxial Growth process and use of the SiC Epitaxial equipment

-Perform cost analysis and vendor comparison

-Analyze and pick top two SiC epitaxial deposition equipment present on the market

[Jan’15 – Dec’15] Research Assistant at Texas Tech University, Lubbock, Texas Implementation of Combinational Multiplier using FinFET Technology

-Designed the 2*2,4*4,8*8 Combinational Multiplier Circuits using HSPice for FinFET technology.

-Compared their delay, power and power delay product for sub, near and super threshold voltages.

-Analyzed the results for 7nm, 10nm, 14nm, 20nm.

Analysis of FinFET and CMOS at Sub, Near and Super Threshold levels

-Implemented basic gates, Adder circuits for FinFET and CMOS technology using HSpice tool

-Calculated the Power, Delay and Power Delay Product for Sub, Near and Super threshold regions.

-Compared the FinFET results with CMOS results for 20nm, 32nm, 45nm technologies.

Standard Libraries for FinFET

-Created the Standard Libraries for all basic gates.

-Implemented for 16nm, 20nm technologies using HSpice tool.

[Oct’14 – Dec’14] Lab Assistant in Program for Semiconductor Product Engineering (PSPE) Laboratory. at Texas Tech University, Lubbock, Texas

Conducting lab tour to a group of 30-40 students in Digital testing, Parametric and Functional testing courses every semester.

Lab safety captain - responsibilities include taking care of lab equipment and help students while they are dealing with the equipment.

Leading a project with team of five in Testing of digital systems course.

Testing of Analog to Digital Converter ADS7800KP

-Tested the TI part on NI-PXI for functionality, continuity, Input leakage, Power consumption, Voltage threshold, skew measurement, conversion time, INL (Integral Non-Linearity), DNL (Differential Non- Linearity), offset error and gain error.

-Used Agilent Oscilloscope, Keithley 2400 source meter, RIGOL function generator for the bench test.

-Successfully verified the results obtained by comparing the datasheet.

-Performed the data analysis and statistical analysis like Cp, Cpk on the measured values using JMP.

-Coding was done in LabVIEW.

Testing of D Flip Flop using NI's Savage

-Designed and built a custom Design Interface Board through PCB layout tool,

-Built a full test sequence from scratch using NI's Test Stand on given D Flip Flop and executed it using STS user interface

-Performed Continuity, Leakage, Functionality, Power Consumption

Testing of Digital IC using Lab VIEW

-Extensive project plan generation and test coverage assessment

-Bench testing of quad 2-input NAND Gate SN74AHC00 to ensure proper functionality of the chip

-Performed Continuity, Voltage Output High/Low, and Power Consumption tests on PXI using LabVIEW

-Cp/Cpk and GRR data analysis using JMP and Microsoft Excel.

ACADEMIC PROJECTS

Common mode Feedback Circuit for Fully Differential Amplifier

-Analyzed and developed the CMFB circuit schematic using 0.6um technology in Cadence Spectre.

-Created the layout in 0.6um technology and successfully checked the DRC, LVS match in Cadence Virtuoso

FPGA implementation of 1024X32 bit Random Access Memory (RAM).

-Designed RAM with 10 address bits and 32 bit word length with Read, Write and Reset access in

-Verilog code in Xilinx ISE.

-Functional verification of complete design by creating test-bench.

Design and Layout of Self biased Operational Amplifier

-Implemented self-biased op-amp with the given specifications.

-Designed Layout, DRS Verification, LVS Check using Cadence Virtuoso

Image Inpainting using Gaussian Pyramid

-It is the technique of filling in the missing region or removing the unwanted object from image.

-Implemented using MATLAB tool.

Course Work

Solid State Devices, Testing of Digital Systems, Advanced Modular Testing Methods for IC, Analog IC Design, Advanced Digital System Design, Introduction to VLSI Design, Introduction to Semi-Conductor Processing.

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