Nidhi Gupta

FPGA Engineer Scrum Master

ad2unl@r.postjobfree.com, +1-336-***-****

LinkedIn Profile: https://www.linkedin.com/in/masters-electronics-guptanidhi/ Current Focus: IP based complex designs, RTL, Simulation, Testbench, Timing Closure Summary:

• 18+ years of experience in design and development of electronic systems based on different target technologies (FPGA/ASIC/SoC/PCB/MCU/CPU)

• Experience of implementing high performance digital designs using on-chip components (IPs), on- chip buses and interconnects (AXI), standard design techniques for timing closure such as Static Timing Analysis (STA) and Clock Domain Crossing (CDC) analysis

• Extensive experience of Intel’s FPGA development EDA toolchain based on Quartus software with integrated tools like Modelsim, signal tap II, system console, platform designer and timing analyzer

• Extensive experience of Xilinx’s development EDA tools with integrated flows for RTL design, high level synthesis and SoC development with embedded processor

• Developed Python scripts for automated verification and validation of FPGA based hardware systems using test-vectors and self-checking testbenches

• Design experience of interfacing FPGA with on-board components including memories (SRAMs, DDR, FIFOs), data converters (ADCs and DACs), MCUs and other discrete components

• Working experience of communication interfaces and protocols such as JESD204B/C, USB2/3, VME, PCIe, UART, SPI, I2C, LVDS etc. for both high-speed and low-speed applications

• Implemented fixed point algorithms on FPGA for image processing functions for medical applications

• Developed GUI based algorithms using object-oriented programming languages such as C# for FPGA implementation and C&A software

• Contributed to multiple R&D projects as developer through mixed signal schematic design, analysis, and PCB layout design

• Proven ability to plan, coordinate and implement scientific projects including highly regulated domains using agile development methodology (Scrum) and HDLC process documentation

• Developed scripts for automated builds of engineering tasks using shell, Make, TCL, Python etc.

• Working experience of code management using SVN/Git for version control and efficient collaboration among team members

• Working knowledge of other project support tools such as Microsoft outlook, Visio, Office, Siemens Teamcenter PLM, Microsoft Teams etc.

• Experience in troubleshooting and debugging of hardware designs using standard lab instruments

(Multimeters, Logic Analyzers, Oscilloscopes, Spectrum Analyzer) and advanced on-chip debugging techniques

• Drafted and reviewed technical documents detailing requirements, specifications, architecture, design, test procedures, and validation of electronic systems of important scientific projects

• Ability to quickly learn new skills and apply them for successful project execution Work Experience:

• FPGA/Firmware Engineer, Danfoss, USA; Oct 2023- Nov 2023

• Staff Engineer, Analog Devices, USA; May 2021- June 2023

• Software Engineer IV, Sterling Medical Devices, USA; Sept 2020- March 2021

• Sr. FPGA Firmware Engineer, BCCUSA-MA, USA; Jan 2020- Aug 2020

• Scientific Officer, DAE (BARC, IGCAR), Mumbai, India; Sept 2005 – Dec 2020 Certification: Certified Scrum Master (CSM)

Education:

• M. Tech. (Microelectronics, VLSI & Display Technology), 4.0, Indian Institute of Technology

(IIT) Kanpur, India, 2005

• B. Tech. (Electronics & Communication Engineering), 3.78, Kurukshetra University, India, 2002 Skills:

Target Technology : FPGA, ASIC, PCB, SoC, CPU, MCU EDA Design Tools/Languages : OrCAD, Protel, LTspice, C, Spice, MATLAB FPGA based designs : Xilinx ISE, Modelsim/Questasim, Altera Quartus, Xilinx Vivado HDLs : VHDL/Verilog, SystemVerilog

Scripting Languages : Python, TCL, Make, Shell

Hardware Interfaces : RS232, USB, JTAG, SPI, I2C, LVDS, PCIe, VME, Ethernet Embedded : 8051 based Microcontrollers (CY7C68013A, AT89C51ED2/RD2), ATmega32, Keil µVision, ARM, AXI, Microblaze, Bare-metal GUI Development : Labwindows/LabVIEW, Visual Studio, Visual Basic/C# Project Management : JIRA, Confluence, SVN/Git

Lab Tools : Oscilloscopes, logic analyzers, DVMs, signal generators, Spectrum Analyzers, and JTAG debug tools

Work Details:

1 FPGA/Firmware Engineer, Danfoss, USA: Oct 2023- Nov 2023 I worked on design analysis of VHDL modules which are part of Xilinx FPGA (Spartan 6) based designs developed for control electronics of Danfoss medium voltage drives. It also involved development of testbenches to verify functionality of sub-modules through simulation. I collaborated with cross-functional teams to install, and use virtual environments using VMware Workstation to streamline development process.

EDA Tools: Xilinx ISE 14.7 (Embedded Edition)

2 Staff Engineer (Firmware Engineering), Analog Devices, USA; May 2021- June 2023 I worked with Analog Devices as a full-time employee at Greensboro, North Carolina. Here, I was associated with PAG (Protocol Analyzer and Generator), which is an internal FPGA program to evaluate JESD204x serial interfaces of high-speed data converters. I worked on all aspects of this program including Python scripts, C# coding and RTL design. The complete PAG test-setup consists of an FPGA based carrier board connected to DUT board using high speed board-board connectors. The FPGA design is a high-speed digital design, which is targeted to Xilinx Virtex Ultrascale+ FPGA, while incorporating on-chip High Bandwidth Memory controller and JESD204 PHY. It is a complex AXI bus based SoC design with custom interfaces for on-board components (microcontroller, clock- generators, EEPROM), and other complex IPs for high-speed data transfer such as DMAs, FIFOs, and high-speed memory (HBM).

EDA Tools: Xilinx Vivado 2018.3 – 2021.2, HDLs: Verilog/SystemVerilog, Scripting Languages: Python, TCL

Main Responsibility/Contribution:

• Initiated team meetings for knowledge transfer while resolving initial bring-up issues

• Reviewed and documented existing Python PAG scripts to identify, and propose modifications for ADS10 based PAG system

• Contributed to system integration testing using on-chip debug IPs (ILA, VIO, HBM monitor etc.) while running PAG compliance tests

• Attended 3 days instructor led training - “Designing with Xilinx Serial Transceivers” to work on high-speed serial links of Gbps transceivers

• Detailed analysis of RTL design using tools integrated in Vivado design suit, including Cadence’s Xcelium based simulation flow for HBM IP, and XSIM based simulation for critical sub-modules

• Testbench development for functional simulation of un-documented sections of the code 3 Software Engineer IV, Sterling Medical Devices, USA; Sep 2020- March 2021 I worked with Sterling Medical Devices as a full-time employee. Here I was involved with development of an FPGA based Image Signal Processing (ISP) pipeline to detect specific patterns in the images of blood samples. This is an SoC (Intel Arria10) based design and focus of work was high-speed streaming interfaces to on-board DDR4 using on-chip memory controller IPs. I contributed to design of sub- modules, VHDL coding, testbench, simulation, and debug on the target board. EDA Tools: Quartus Prime Pro 19.3.0, Modelsim; HDLs: VHDL, Scripting Languages: Python, TCL 4 Sr. FPGA Firmware Engineer, BCCUSA-MA, USA; Jan 2020- Aug 2020 As a Senior FPGA Firmware Engineer at ASML Wilton, Connecticut, I played a key role in firmware development for motion control system of EXE5000. While being a member of the electronic development team, I developed a custom BiSS-C Master interface tailored for reticle stage. I completed this activity incrementally and iteratively while finalizing details through multiple interactions and collaboration within the company. As a developer, I took charge of improvising existing VHDL design and testbench code of SIOB, specifically for integrating the BiSS-C master interface of the absolute position encoder. This involved tasks such as preparing a preliminary investigation report, high-level block design, RTL design, VHDL coding, and simulation of the BiSS-C master. EDA Tools: Intel Quartus Prime SE 17.0, HDLs: VHDL, Scripting Languages: Python, TCL 5 Scientific Officer, DAE (BARC, IGCAR), India; Sept 2005 – December 2020 I worked on different types of electronic instruments with application-specific requirements. My work involved mixed signal designs with data converters and other front-end signal processing functions which interface with FPGAs/microcontrollers to buffer and transfer real-time data to PC. As part of electronics groups, main focus of my work was to analyze existing instruments to develop novel architectures for FPGA implementation. It involved all aspects of electronics engineering including FPGA based board design, RTL design, simulation, GUI based algorithm development, system integration and technical support. I contributed as a consultant/developer/scrum master on high-impact projects aligned with long term organizational goals and objectives. I also made important contributions to the design and development of low noise front-end ASIC for X-ray detectors. EDA Tools: Xilinx ISE 12.3, Modelsim XE 12.3, Keil µVision 3, Orcad 14.0 (Schematic Capture, pSpice, Allegro/PCB Designer), Mentor Graphics (DA-IC, Eldo, IC-Station), Tanner, Matlab HDLs: VHDL, Verilog; Programming Languages: Visual C#, Embedded C New Products Developed:

• FPGA based multi-channel DAQ instruments with standard PC interfaces such as USB, Ethernet, PCIe for multiple applications

• FPGA based single-input pulse arrival time recording module for raw data analysis of co- incidence neutron counter for scientific applications

• FPGA based single input DAQ Module with USB interface for multiple applications

• FPGA based MCS for spatial distribution profiling of radio-activity in a drum

• VME bus Simulator and VME bus Interface Controller

• FPGA based MCS with standard features for fluorescence studies Main Responsibility/Contribution:

• Proposed and implemented modular design technique to support iterative and adaptive hardware development based on custom boards

• Contributed to requirement analysis, electrical specifications, interface definition, and protocol selection of many complex systems

• Contributed to high-level architecture, modelling, simulation, integration, verification and validation using improved methodologies and practices

• Identified digital processing functions to be implemented on FPGA, and developed conversion algorithm to replace glue logic of legacy instruments

• Developed detailed logic (RTL) design and IPs for synthesis, implementation, debugging and testing using available FPGA based boards and EDA tools

• Developed test plans and created test-benches to simulate HDL designs at various abstraction levels of a complex design

• Developed firmware for on-board microcontrollers for data transfer and control using standard PC interfaces such as USB, Ethernet, PCIe for multiple applications

• Developed custom protocols for interfacing FPGA with other onboard components such as microcontrollers (8051 series), FIFOs, ADCs, DACs, SRAMs and SDRAMs etc.

• Developed application specific data analysis algorithms for integration with GUI for both real- time and offline data acquisition and control

• Detailed technical documentation of software requirement specifications including user interface for PC based application software

• Completed schematic entry, BOM and PCB layout (4 layers) of complete MCS design with FPGA, microcontroller, FIFOs, comparators along with other components using OrCAD tools

• Market survey, cost-estimation, component’s procurement, co-ordination with assembly group and initial POC demonstration in an existing detector set-up

• Contributed to lab demonstrations, field trials, publications and presentations

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