Princekumar B. Kothadiya Email: ad2ubi@r.postjobfree.com

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SUMMARY

• Results-driven and highly motivated Electrical Engineering graduate student with a strong academic background and hands-on experience in Analog and RFIC design and digital design with skills of VHDL, Verilog and Cadence Virtuoso tool. EDUCATION

California Institute of Technology (CALTECH), California, USA. CGPA:4.2/4.3 MS, Electrical Engineering June 2023

Indian Institute of Space Science and Technology (IIST), Kerala, India. CGPA: 9.59/10.0 B. Tech, Electronics and Communication Engineering May 2022 EXPERIENCE

Undergrad Research Thesis work [PPT][Report] IIST

Mentor: Prof. Immanuel Raja Spring 2022

– Successfully designed, simulated, and layout-ed a 28 GHz Wideband Power Amplifier for 5G mmWave band continuing the work from internship with achieving impressive results including 7+ GHz bandwidth, 14 dB gain, 11.5% PAE, and 14.46 dBm output power at 1.5 V supply voltage using UMC 65 nm Technology using advanced techniques such as Class-J biasing, RC Feedback, Cgd neutralization, and inductive neutralization in Cadence Virtuoso. Undergrad Summer Research Internship [PPT] [Report] IIST Mentor: Prof. Immanuel Raja Summer 2021

– Led the completion of the schematic design for a 28 GHz Wideband Power Amplifier for 5G application in UMC 65 nm Technology using Cadence Virtuoso software, achieving 12.9 dBm saturated output power, 8+ GHz 3-dB bandwidth, almost 18 GHz wideband matching, and 19% peak PAE in simulation. SKILLS

• Programming Languages: Python, C++, Verilog, VHDL

• Utilities: MATLAB, Xilinx Vivado, Cadence Virtuoso, Intel Quartus, Questa, LTSPICE, ADS, Ki-CAD, PyTorch, LATEX

• Relevant Coursework: Analog VLSI Circuits design, RF Integrated Circuit Design, Digital Circuit design with FPGA and VHDL, Advanced Sensors and Interfacing Electronics, Machine Learning and Data Mining RELEVANT PROJECT WORKS

Analog and RF Integrated Circuit Design Projects

Low power Noise cancelling LNA Designs at 860 MHz in CMOS UMC 65 nm [PPT] IIST Two-stage rail-to-rail differential 76 dB OTA design with CMFB and 63 of PM in CMOS SCL 180 nm [PPT] IIST Multi-stage resistive feedback 6.26 GHz TIA design with 50 Ohms load drive in CMOS 45 nm [Report] CALTECH Digital Design Projects

Tic-Tac-Toe (X-O) game design with VGA and Keyboard interfacing in Verilog [Github] [Report] IIST Static and Dynamic image using VGA interfacing on Intel Altera Cyclone V FPGA in VHDL [Report] CALTECH PWM Audio Amplifier on CPLD Xilinx XC9572 in VHDL [Github] CALTECH 16-bit Serial divider using non-restoring algorithm on CPLD Lattice ispMACH4128ZE in VHDL [Github] CALTECH ACHIEVEMENTS & COMMUNITY ENGAGEMENT

• Received Certification for completing the Integration and Design of Space Vehicle (IDSV) course taught by Dr. B N Suresh, the IIST Chancellor and an honorary distinguished professor at ISRO.

• Received Satish Dhawan Endowed Fellowship for MS in Electrical Engineering at CALTECH for academic excellence

(Rank-2, CGPA-9.59/10.0) in undergraduate.

• Received Semester Fees Assistantship and Book Grant for maintaining CGPA above 7.5/10.0. throughout the 4 years of undergraduate studies.

• Nominated for Innovative Student Project Award 2022 by INAE for undergrad research project work project.

• Worked as a Coordinator @ IIST in Finance and Events team of Annual Cultural Fest Dhanak and Annual Technical Fest Conscientia in 2018 and 2019.