MATT MOSHIR

P.O. Box ******, San Diego, Ca. *****

ad2pw9@r.postjobfree.com 619-***-****

U.S. Citizen

Resume date: 12/13/2023

Senior FPGA, SoC and ASIC Design and Development Hardware Engineer

(not looking for a: ‘Verification-only’, ‘Test-only’ or ‘software-only’ engineer role)

Career preference: Available for offsite or partially remote roles nationwide.

Profile Summary:

A Senior FPGA, Soc & ASIC Design Engineer with 18+ years of extensive expertise & experience in FPGA, hardware design, embedded hardware systems with demonstrated development accomplishments.

Broad range of experience across electronics and advanced-technology industries, including aerospace satellite communications and automotive ASIC designs with ADAS and ASIL requirements.

Expert in high speed, high density FPGA design and development, SoC and ASIC design, simulation, verification, RTL development and synthesis, Xilinx (AMD) and Altera (Intel) FPGA tools, platforms and technologies. Experience with ZYNQ UltraScale+ MPSoC, HPS, and other embedded systems.

Proficient in Timing Analysis, SDC, slack, setup, hold, false path and constraint development.

Familiarity and experience with SVN, Git, Github, BitBucket, Git Bash, Cloning, Branching, Commit, Push and other commands.

Extensive experience and familiarity with wide variety of hardware and software development tools both in Linux and Windows environment, FPGA and CPLD tools, schematic and layout tools, analog and digital circuit design tools.

Expert in complex electronic circuits and board designs, circuit simulation, prototype, system bring-up, debug and test.

Able to come up with quick solutions for wide range of new designs, taking advantage of knowledge from past experience resources and design works including VHDL, Verilog, ‘C’ and Assembly resources.

Clear background and able to obtain Clearance.

Proficiency and skills in Microsoft Office tools (Word, Excel, PowerPoint, Outlook, Visio, Project).

Holding a USPTO granted personal patent in 2012, as well as a certificate for an Advanced Altium Designer course completed in 2017.

Personal skills:

Strong organizational skills and attention to details. Professional attitude and demeanor.

Ability to multi-task in a fast-paced environment, fast learning, with short and quick ramp-up.

Strong verbal, written, computer and technical communications.

Ability to work independently and as a team member.

Versatility and flexibility to work within constantly changing priorities with enthusiasm.

Thorough understanding of electronics technologies, products, equipments, processes, engineering concepts and practices.

Hardware skills:

Development tools: I have designed and developed high density FPGA logic circuits using the following tools and IDEs: Xilinx tools: Vivado2018.2, ISE14.7, PlanAhead, iMPACT, PACE, Coregen, ChipScope, PinPlanner. Intel (Altera) tools: Quartus II 20.3, Platform Designer, Timing Analyzer, SOPC Builder, Qsys, MegaWizard PLL gen., SignalTap, Component Editor. Lattice tools: ispLEVER, Diamond. Simulation tools: ModelSim PE10.4, QuestaSim64 10.4d, SynplifyPro, Simulate, Stimulus Editor and Viewer, Misc tools: Emacs editor, Notepad++.

Performed and implemented RTL Synthesis, Testbench development, timing analysis and closure, emulation, debugging, simulation, verification, and worked with V-Metro modules, xdc, ucf, qsf, SFL (Serial Flash Loader), Altera Avalon I/F and AXI4, SRA, PRA bus systems.

Circuit design tools: Altium Designer, ORCAD Sch. Capture and Layout, Pspice, PADS, PCAD, LTSpice.

Hardware languages: Extensive familiarity and experience with VHDL, Verilog and TCL scripts.

FPGAs: Experience with Xilinx Virtex UltraScale+, ZYNQ UltraScale+ MPSoC, Virtex 7/V/IV, Kintex7, Spartan 6/3, Intel (Altera) Stratix10 SoC, Cyclone IV GXB, Stratus, Flex10K, Lattice Mach4000, as well as CPLD, PAL, GAL and EPCS configuration FLASH.

Hardware components: I have worked with a wide variety of electronic components, transducers and sensors including: MOSFET and FET transistors, LDOs, voltage regulators and switching supplies, OpAmp, Tyristor, Triac, Thermopile Laser sensor, Zener, Laser diode, LED, PIN diodes, Thermocouple, Optocoupler, CMOS, Piezoelectric and Hall sensor, GMR, …

Hardware interfaces and communication techniques: hands-on experience and familiarity with: PCIe, XAUI, USB PHY, Aurora, Ethernet, EtherCAT, RFCB (RF Control Bus), LVDS, HSS, I2C, SPI, Camera Link, DSP, PLL, VCO, DDR, ADC, DAC, IF, Baseband, PXIe, AXIe, ...

Lab tools: Aerospace Test Sets with modular racks and chassis, Keysight, Tektronix and HP logic analyzer, Infiniium digital oscilloscope, spectrum analyzer, power analyzer, Signum JTAGJET, AVR JTAGICE, IAR jlink, Xilinx JTAG, Qualcomm CDP.

Software skills:

Processors and embedded controllers: Developed software for Qualcomm Cell Phone MSMs including: Waverider, Aragorn and Gandalf, with ARM9, ARM7 and Cortex. Experience with Atmel Atmega, TI MSP430, PowerPc MPC860, PIC processors: PIC12C509A/PIC16F874/PIC16F887/PIC18F2525, Altera NIOS II embedded controller, OMAP.

Software languages: ‘C’ and assembly programming in UNIX/Linux or Windows. Extensive experience with ‘C’ Compiler, Linker, Assembler, Make, Script and RTOS. Written more than 100k lines of ‘C’ and Assembly programs.

Compilers and IDEs: Have experience with IAR IDE, AVR Studio, Microchip MPLAB, CCS PCW and C32 ‘C’ Compilers, Microcross Visual X-Tools, winAVR, C-SPY, XLINK linker

Debugging and Software tools:, EDS (Embedded Design Suite), Eclipse and BSP Editor, Chameleon ICE, FLASH programmer, Boot Loader, SAM-BA, AT commands, Teraterm, TRACE32.

Written device drivers for: SDRAM, FLASH, SRAM, FIFO, EEPROM, I2C, SPI, USB, EP, Dallas 1-Wire, UART, PCI, QSFP, PWM, DMA, File System, Partition, Segmentation, Cluster, Sector, MBR (Master Boot Record) & PBR, FAT, lun

Experience with SVN (SubVersion), SOS, ClearCase, ClearQuest, Cleartool, Reflection Revision control, Citrix.

Academic Qualification: University of Science & Technology (B.S.E.E.) Electrical Engineering, Tehran, Iran

Experience:

Senior FPGA Design and Development Engineer – Personal Research and Development – Serialight – Jun. 2023 – Dec. 2023

Research and development of QSPI 8wire (6/4bit) interface, in Linux environment, running on Intel Arria platform, using Quartus and platform designer. Compilation and integration was performed in Cadence Virtuoso environment using make files and simulation implemented in SimVision. Test bench .sv files were developed and generated in Emacs and Vim. Created and developed Tx and Rx FSMs.

Senior FPGA, ASIC and SoC Design and Development Engineer – Direct Remote Position – Synapse Design Automation (Quest Global) – Nov. 2021 – Sep. 2022

Participated in design and development of custom ASICs with ADAS capable and ASIL B/D qualified Automotive zonal and domain ECU systems and performed prototype design and research on implementations, through Xilinx ZCU102 platform with embedded Zynq UltraScale+ MPSoC FPGA. Evaluated a design implementation with very details of Zynq PS, PL, APU, RPU, CSU (Configuration Security Unit), PMU, DDR, DMA, CAN, SPI, PCIe, GTR, MIO/eMIO and feature-rich programmable Logic interfaces and capabilities.

Created and designed many system level block diagrams including solutions for next generation automotive custom SoCs, and provided presentation slides for prominent major automotive industry clients, provisioning very high throughput multi-processing systems including heterogeneous compute Cortex-A53/R52, Cortex-M7/R4 processors, ARM Mali ISP, AXI4, FlexRay, CAN-FD, GEM, PCM (Phase-Change Memory), GPU, …

Involved in research and review of many new advancements in ASIC and SoC developments by: NXP, ST, ARM, Nvidia, Renesas, Xilinx, Intel, Visteon, Infineon, and others.

Worked with clients and vendors for design and development of SiP (System in a Package) using TI MSP430 MCU Die.

Ran Vivado and Cadence programs through VNC and VPN in Linux.

Senior FPGA Design and Development Engineer – Contract Partially Remote Position – Northrop Grumman – Sep. 2018 – Jan. 2021

Satellite communications systems:

AEHF and PTW Waveform and Uplink/Downlink Frame and packet development.

Experience and familiarity with Security and Anti-jammer aspects of satellite communications systems

including: TRANSEC, PTW, Frame formatting, Cover/Decover, AES, Permutation, Hopping, Rotation,

QPSK, BMC, Modulation, Interleaving, ICP-ICD, SG-ICD, PTW-ICD, EQ4-Specs.

Acquisition, tracking, logon, telemetry, terminal timing probe and probe response.

Worked on a Spacecraft WMU (Wideband Modem Unit) project.

Worked on Spacecraft Comm-PLY SDU (Switch Demod Unit) and CU (Control Unit) Testsets.

Involved in a Missile engine control unit design and development.

Participated in development of CTU (Command Telemetry Unit), CFU (Command Formatter Unit), CSU

(Command Subdecoder Unit).

Developed Ethernet PCS/PMA interface with SGMII to PHY through SelectIO LVDS I/F and with GMII to MAC for Virtex UltraScale+ FPGA on Xilinx VCU118 development platform, in Vivado 2018.

Developed Ethernet UDP Control Plane frame processor with AXI-S, MAP (Memory Access Protocol), FIFO9x4k, LinkLocal, Ethernet Frame Demux/Decoder, and Register File interfaces. Worked with CPP (Control Plane Processor), and SoC with MicroBlaze and SDK.

Developed 10Gbit/s XAUI interface through GTY/GTH Transceiver, FMC+ and HTG.

Generated 10 GbE (Gigabit Ethernet) SFP interface @ 156.25 MHz

Developed VHDL RTL for Virtex7 UltraScale+ on Xilinx VCU118 platform and worked with Verilog IPs.

Also developed RTL for Virtex7 on Xilinx VC707 platform.

Created projects in Vivado 2018.2 and ISE 14.7. Compiled Xilinx libraries.

Synthesized and Implemented designs running PAR, and generated .bit bitstream outputs.

Instantiated and generated components and modules. Generated .xdc files and defined constraints.

Automated simulation through .do scripts using TCL commands, Vmap, Vlib, Vcom, Vsim, wave.do …

Created compile and file lists. Used Emac, Notepad++ and VI.

Generated test bench and Stimulus with 8b10b and K-Char symbols for Ethernet UDP packet generator and monitor. Included clock generation, clock divider, reset sync and delay functions.

Simulated and verified the design in Linux using QuestaSim64 10.6C

Involved in very details of BITSLICE and BITSLICE_CONTROL nibbles of SelectIO during simulation.

Generated FIFO, XAUI with 64 bit rxd/txd and rxc/txc xgmii interface, 10Gb XGMII, ten_gig_eth_pcs_pma, and other IPs using CoreGen.

Using Xilinx LogiCore, instantiated 10GBASE-R Ethernet PCS/PMA interface with MAC through XGMII on one end and PHY (PMD – Physical Medium Dependent) on the other.

Experience with KeySight AWG and PCIe.

Worked with Exceed-On-Demand, Tortoise SVN, Office tools and lab tools.

Worked with Quartus Pro, Platform Designer, TimeQuest Timing Analyzer and Avalon ST/MM on another project.

Generated VHDL Entity, Architecture, process, procedure and function.

Developed VHDL in ISE 14.7 using CoolRunner II CPLD for a missile engine control project.

Developed SPI Master and Slave modules. Designed several FSM engines with Register access.

Participated in many design reviews, presentations and meetings.

Senior FPGA Development Engineer – Contract Remote Position – CurtissWright, Jul. 2017 – Nov. 2017

Developed VHDL and Verilog RTL code for Boeing SDR (Software Defined Radio). Integrated PCIe Gen2/Gen3 x8/x4 interfaces into HDK for VPX3 with Xilinx Virtex7 FPGA in Vivado 2015.4 IDE. Instantiated Aurorax4 64B/66B core with AMBA AXI4 Stream and Frame interface. Created and integrated FusionXF Capability framework, with SRA interface. Used Vivado Power Analysis and XPE (eX Power E) tools for power analysis. Developed and integrated heater function with BRAM and DSP Slices. Created interfaces for HSS LVDS, with LVTTL user I/Os and GTX/GTP running at 5.0 Gbps. Created design hierarchy through TCL scripts and structure modules. Integrated FPGA Heater Function into HDK. Developed interface for XADC temperature and voltage monitor with I2C I/F. Integrated ADC and DAC interfaces, along with Checker and Generator. Integrated DRS SI9172 VPX3 Tuner with Aurora interface into XF07-523 XMC card. Created register map and made connections and access through FusionXF Capability. Created demo slide document in ppt. Wrote user manual.

Created testbenches and test scripts for Chipscope_SRA and PCIe accesses through SDK and Host. Developed, instantiated and simulated NWL (NorthWest Logic) PCIe BFM interface. Simulated designs with Metro Graphic Questasim64_10.4d, as well as ModelSim PE 10.4. Used TCL for simulation.

Compiled Xilinx libraries. Created project through TCL scripts. Also used TCL for compiling design libraries. Built, synthesized, placed, routed and implemented design, through TCL scripts in batch mode, and generated bitstream .bit FPGA image. Created Filelists and type Records in pkg modules. Defined Generics and Constants in VHDL modules. Created design file structure hierarchy and libraries including synthesis, implementation, vm libs, source and constraints paths. Defined environment variables and managed licenses. Integrated XDC and UCF constraint files through TCL commands.

Created and integrated interfaces for DMA engine, DDR3 SDRAM, FIFO, C2S (Card to System), S2C (System to Card) and high speed SerDes. Developed interfaces to Board Support IP (BSIP) containing PCIe, DMA Engine and MTTE. Used FPGA resources LUT, CLB, FF, DSP, Slice, Tiles.

Senior Electrical Engineer – Avvatek - Personal Research and Activities – San Diego, CA. Apr. 2016 – Jul. 2017

Participated in an Advanced Altium designer course provided by Altium and obtained an Altium certificate in 2017.

In that advanced course, I learned or refreshed my experience about the subjects including, but not limited to: Differential Pair Routing, High Speed Design, Length Tuning and Calculations, Impedance Controlled Design, Design Directives, Polygons, Hierarchies, Project Management, rigid-flex PCB, Board Shape Design, Layer Stacks, Netlist, Placement, PCB Panel, Design Rules, Clearance Rules, DRC, Blanket, Classes, Nets, Rats Nests, Query Helper, Query Builder, 3D, Keepout, Cutout, Vertices, Via Stitching, Track Slicing, Teardrops, Testpoints, Assembly and Fabrication Testing, Pad and Via, Legend, Drill Pairs, Graphic Images, Logo, Barcode, Design Views, Output Job Generation, Gerber, Embedded Board Array, Inspector Panel, V-Score, V-Groove, Grids, Sheets, Template, Title Block, Mechanical Layers, Schematic and Layout Libraries, BOM, Project Management, Version Control, SVN, Repository.

Research and experiments with nVidia Jetson TX1 HDK carrier board, including Tegra CPU, GPUs, DDR3, USB3/2, HDMI, SD Card, PCIe, DSI, eDP, CSI, Ethernet, GPIO, JTAG and other interfaces.

Senior Electrical Engineer – Contract Position – Covidien, Carlsbad, CA. Aug. 2015 – Apr. 2016

Designed and Developed control board circuits in Altium Designer 15, including both layout and schematic circuits such as: USB 2.0 ULPI PHY HOST controller, USB HUB, Ethernet I/F, OMAP, DVI and HDMI interfaces and control circuits, EEPROM SPI and I2C interfaces, FLASH memory, LPDDR SDRAM, UART, ESD Filters and Level Translation solutions, LDO and Buck Regulators.

Proficient and skilled in very details of Altium IDE tool suite. Generated Fab and Assembly output files, and documented them in Agile system.

Troubleshooting root cause of failures as recorded in JIRA tasks. Participated in design reviews and meetings. Passed many medical devices trainings as well as FDA courses and received corresponding certificates. Loaded and configured BL (Boot Loader), OS (Operating System) and Application programs to control boards through MMC based Debug board, TeraTerm and utility programs, using SD card and FLASH.

Worked with QuestaSim, ModelSim, Quartus, Virtex-7 FPGA, and Office Tools.

Research and Development – personal project – San Diego, CA. Jan. 2014 – Aug. 2015

Development, implementation and prototyping of a personal patent granted to me in 2012 by USPTO.

Wrote, synthesized, programmed and tested VHDL modules in Lattice ispLEVER environment and prototyped the design using ispMACH4000. Simulated modules in ModelSim PE. Designed and developed CMOS Layout in Electric environment.

Developed ‘C’ and “Assembly” programs in MPLAB for Microchip PIC18F2525 and PIC16F883.

Senior Electrical Engineer – Contract Position – Qualcomm, San Diego, CA. Jul. 2012 – Jan. 2014

Partial integration and verification of Qualcomm MSM chips including Waverider, Aragorn and Gandalf.

Wrote ‘C’ source code and CMM scripts in Linux for KPSS (Krait Sub-system - ARM7/9 based controller), SPDM (System Profiling and Diagnostic Monitor), and VI automated regression routines.

Created and managed ClearCase View, Task, Activity, Elements, Checkout and checkin.

Worked with Trace32 Debugger, Veloce, CMM scripts, QSPR (Qualcomm Sequence Profiling Resource), Qwebstats (Qualcomm's web-based test reporting system), ClearCase, ClearQuest, Cleartool, Citrix, RPM (Resource Power Management), PMIC, Xerxes power controller and monitor system, CDP (Core Development Platform), and TCU (Temperature Controller Unit).

Troubleshooting, debugging and analyzing PVT (Power, Voltage and Temperature) tests.

Learned many complicated aspects of cellular phone blocks, systems and related development tools.

Senior Hardware Design Engineer – Contract Position – Nordson, Carlsbad, CA. Jan. 2012 – Aug. 2012

Wrote VHDL and Verilog for Xilinx Spartan6 FPGA.

Synthesized, implemented, and programmed FPGA in ISE, and performed Floor planning, layout, PAR and verification of module blocks.

Simulated HDL in ModelSim PE and used Chipscope for debugging through Xilinx JTAG Interface. Designed FPGA circuits. Created and managed PCB and Schematic library components in Altium Designer IDE. Generated component footprints and schematic symbols.

Created PCB layout, and implemented routing, part placement, back annotation, cross-probing. Generated output and Gerber files. Defined board shape, keepouts, layer stacks, high speed differential signal routing and tuning, and design rules.

Created projects, workspace and SVN subversion version control. Managed document and design file control within embedded SVN control.

Created components and views in 3D. Inspected and verified board and layout in 3D view.

Debugged, verified and tested prototype board, using oscilloscope and logic Analyzer, JTAG dongle and debugger. Implemented, tested and verified Ethernet/EtherCAT IP core and automation control system through Beckhoff TwinCat hardware and software interface.

Senior FPGA Design Engineer – Contract Position – Ethercomm, Carlsbad, CA, Feb. 2011 – Sep. 2011

Developed and designed Altera Cyclone IV FPGA system in Quartus II environment for RF Radio Transceiver with high speed LVDS RFCB (RF Control Bus) interface.

Created NIOS II, code memory, FLASH, SPI, USB and I/O interfaces with Avalon bus in SOPC Builder. Generated new interfaces in Component Editor. Wrote VHDL, Test Bench and TCL scripts for simulation in ModelSim. Debugged the design in real time using USB-Blaster with SignalTap and EDS debugger. Wrote operating system, control and monitoring ‘C’ functions and routines in EDS environment for NIOS II processor and created interrupt routines in ‘C’.

Generated HAL API BSF and FLASH programming files from sof. Programmed EPCS using synthesis sof and jic outputs, SFL and Quartus programmer. Designed and developed SLS USB using UTMI and ULPI interface.

Designed FPGA schematic in PADS and wrote related VHDL hardware.

Senior FPGA Design Engineer – Contract Position – Curtiss-Wright, San Diego, CA, May. 2008 – Aug. 2010

Developed VHDL & Verilog modules in ISE 11 for Xilinx Virtex5 FPGA. Created Testbench and simulated the design using ModelSim pe 6.5, and TCL (Tool Command Language) scripts. Used Vsim, Vcom and Vlog in TCL and Do commands. Created and managed libraries.

Tools used in development: Coregen, iMPACT, PACE, Wave, Stimuli, ucf, JTAG, Emacs editor, Teraterm terminal, putty, Reflection Linux bridge, SAP document system.

The following are a brief description of the modules and materials I have worked with:

HDK (Hardware Development Kit), I2C, Config EEPROM, PLDA BFM, GTP PCI express x8 and MGT PCIx, Link Core, SERDES, DMA controller and FIFO, FusionXF Capability, sFPDP (serial Front Panel Data Port) Fiber channels, DDRII SDRAM, TX & RX FIFO, vm V-Metro library and modules, BSIP (Board Support Intellectual Property), PMC (Processor Mezzanine Card), XMC, ADC512 AD Converter FMC (VITA 57.1 FPGA Mezzanine Card), 1000MSPS FMC-520 DA Converter, LVDS RIO (Rocket I/O) Interface, FPE320 3U VPX FPGA Processor Mezzanine site, HSS Diff.Pairs, backplane.

FPGA programming in ISE through Xilinx Parallel Interface Cable IV, and test of JSM module by Xilinx iMPACT, CorEdge BIOS debugger, Intel 82571 Gigabit Ethernet Controller, JTAG chain.

Senior Firmware Engineer – Contract Position – Luxtera Inc., Carlsbad, CA, Sep. 2006 – May 2008

Developed firmware in IAR Embedded System IDE for AT91SAM7S256 ARM7 based controller, used in 10 GBPS optical system. Wrote ‘C’, and Assembly routines for isr, SSC, SPI, 1Wire Temp. Sensor, QSFP I/F, Flash loader, parsing, .mac, cStartup, UART, I2C Master/Slave. Used Mathlab and LabView during the development. Worked with SAM-BA, configuration, debugger, Jlink JTAG ICE I/F, CSPY, XLINK.

Developed QSFP and I2C slave Verilog code in ISE for Xilinx Spartan3.

Senior HW and Firmware design Engineer – Direct Position – General Atomics, Jan. 2005 – Oct. 2006

Designed and developed 12 layer AT92RM9200 ARM9 based controller board with 180MHz PLL, interfacing 580MHz A/D and UWB RX/TX using PCAD 2004. Code development, ARM9 debugging and programming using Microcross X-Tools Compiler, Linker, GNU “as” Assembler, Make, Script, Signum JTAGJET, Chameleon ICE and FLASH programmer. Incorporated the following modules, components and devices into the design: Xilinx Virtex IV FPGA, ARM9 controller, SDRAM, serial Asynchronous FLASH, parallel FLASH, SRAM, JPEG2000 controller, CCD timing controller and interface, Camera Link controller, Power Supply, USB I/F, RS232. Designed and developed VHDL modules for Virtex IV FPGA using ISE8, PACE and iMPACT programmer, Xilinx JTAG, Synplify, RTL synthesis, Timing analysis.

Created system flowchart and block diagrams. Wrote specification documents, …

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