Post Job Free

Resume

Sign in

Hardware Design Systems Engineering

Location:
Tulsa, OK
Posted:
January 04, 2024

Contact this candidate

Resume:

LAXMA REDDY CHITTAPUREDDY

+1-346-***-**** ad2gju@r.postjobfree.com Tulsa, OK 74133

https://www.linkedin.com/in/laxma-reddy-chittapureddy-663934117 https://github.com/laxmareddy2803

EDUCATION

Master of Science in Computer and Systems Engineering (GPA: 3.3) Aug 2021-May 2023 University of Houston, Houston, Texas

Bachelor of Engineering in Electronics and Communication Engineering (GPA:3.6) Aug 2016-Sep 2020 Osmania University, Matrusri Engineering College, Hyderabad, India COURSEWORK

Switching Theory and Logic Design, Analog Electronic Circuits, Digital Electronics, Digital Signal Processing, Digital System Design with Verilog HDL, Micro Processors and Microcontrollers, Embedded Systems, Advanced Computer Architecture, VLSI Design, Advanced Hardware Design

SKILLS

Hardware description languages : Verilog, SystemVerilog, VHDL Verification methodologies : SystemVerilog, UVM

Scripting languages : Python, Perl

Tools : Cadence Virtuoso, Xilinx Vivado design suite, Questasim, EDA playground, Mentor Graphics tool

Communication protocols : I2C, UART, SPI, CAN, USB Bus protocols : AXI, AHB, APB

Other : C, RTL2GDSII flow, Static Timing Analysis, Functional coverage, Code Coverage, Assertions, DFT, GIT, Oscilloscopes, Logic Analyzer, Constrained Random Verification, BIST, ATPG, Scan Chain, Windows, Linux, MacOS EXPERIENCE

Electronics Engineer, Mingo Aerospace Nov 2023-present

• My job responsibility includes specializing in efficient PCB troubleshooting using oscilloscopes, logic analyzers, and digital multimeters. Proficient in schematic analysis and firmware debugging, with a keen ability to collaborate cross- functionally.

Instructional Assistant (Advanced Hardware Design), University of Houston, Houston, Texas Dec 2021-Dec 2022

• Assisted instructor in organizing course materials for Advanced Hardware Engineer class with 40 students.

• Guided students in designing digital systems, enhancing communication of technical ideas verbally and in writing. Intern, Robo Art Embedded Solutions Pvt Ltd, Hyderabad, India Nov 2020-Feb 2021

• I had the invaluable opportunity to contribute to cutting-edge technological advancements by working on a project centered around DTMF-controlled home appliances. With a strong focus on both hardware and software aspects, I meticulously designed circuitry and programmed microcontrollers to interpret DTMF signals, enabling seamless control of various household devices.

ACADEMIC PROJECTS

Design and Verification of UART Communication Protocol using SystemVerilog Fall 2022

• Engineered a SystemVerilog-based UART protocol, encompassing transmitter and receiver modules, baud rate generation, framing, and error handling.

• Developed an intricate testbench in SystemVerilog, integrating UART protocol design, stimulus generation, and functional coverage through generator, driver, monitor, scoreboard, and interface classes. Design of 1-bit ALU Circuits using Cadence Virtuoso Tool Fall 2021

• The object of this project is to get familiar with the design of 1- bit Arithmetic Logic Unit (ALU) and Cadence virtuoso tool as part of the VLSI design course work. The idea is to perform basic arithmetic and logic operations on 1-bit inputs and involves schematic creation, logic design, layout implementation, and simulation within the Cadence Virtuoso environment.

Design of low power R2R ladder DAC for high-speed communication using Mentor Graphics Tool. Aug 2020

• Designed a better and power efficient DAC for high-speed communication. The digital architecture of the project verified on the Mentor Graphics Tool.

• Designed an op-amp, R-2R ladder as the components for efficient work of Digital to Analog converter. CERTIFICATIONS

• "The Complete Python Bootcamp from Zero to Hero in Python" by Jose Portilla on Udemy

• "VLSI Design Methodologies" by Maven Silicon

• "Perl 5 Essential Training" on LinkedIn Learning

• "SystemVerilog for Verification" by Kumar Khandagle on Udemy

• "UVM for Verification" by Kumar Khandagle on Udemy

• “VSD-Static timing Analysis” by Kunal Gosh om Udemy



Contact this candidate