Simran Kaur Sidhu

Dallas, TX ad13en@r.postjobfree.com

IC Layout Engineer 559-***-****

Profile:

● 5+ years of collective experience in analog, digital IC mask layout design.

● Working as an Analog Layout engineer at IC Enable LLC. [ Nov 2020 – Present]

● Graduate student assistant at California State University Fresno. [Jan 2018 – May 2020]

● Experienced in RF, cmos technology and in advanced finfet technology.

● Proficiency in EDA tools cadence virtuoso, assura and mentor calibre.

● Basic knowledge about Cadence Skill scripting to improve productivity.

● Strong verbal and written communication skills.

Education:

● MS in Electrical & Computer Engineering California State University Fresno CA GPA: 3.7 May 2020

● B. Tech (Electronics & Communication) from Guru Nanak Institutions Technical Campus GPA: 3.6 May 2017

Skills:

Tools: Layout: Cadence Virtuoso (L, XL, ADE-L and ICADV), Mentor Graphics. DRC and LVS: Assura, Calibre. HSpice simulations.

Programming Languages: Verilog-A, Basic Python, Basic C/C++, skill scripting. Ms-office suite: Excel, PowerPoint, Word, Notes.

Layout skill set:

1. Expertise in finfet and cmos layout of OPAMP, LDO, ADC, DAC, PLL, DLL. 2. Good understanding of various parasitic effects and minimization techniques. 3. Knowledge of circuit functionality to understand the requirements 4. Expertise in taking care of deep sub-micron effects like LOD, STI, WPE 5. Experienced in handling reliability issues such as ESD, EMIR, LUP and antenna. 6. Experienced in various matching techniques for resistor, cap and mos. 7. Efficient methods to fix LVS, DRC, Latch up, Antenna errors in short time interval. 8. Expertise in Block schedule planning, execution. 9. Proficient in using VXL tools like annotation browser, extract layout, clear logical connectivity, propagate nets, wire assistant.

10. Knowledge of STA and tools used for verification. Experience:

Texas Instruments [July23 – Present]

As a contractor through IC enable, Working in Analog test chip development. Responsibility: Interpreting the device spec sheets and through them Implementing complex analog device type Layout using hybrid approach (manual and skill coding) and verification flow including LVS, DRC.

Challenges: Adapting to, and implementing frequently changing Design rules, as with every test chip project, the DRC deck keeps changing. Quick getting aquatinted with different device parameters.

Micron Technology (DRAM) [Sep 22 – June23]

As a contractor through IC enable, Working in ASIC Analog and Digital critical sub-blocks, power grid network.

Responsibility: Implementing Layout and verification flow including LVS, DRC, ERC and interpreting the results from the Cadence Virtuoso Verification suite. Implementing ECO in the hierarchy to top chip level. Identifying quality and reliability improvements in IC circuit and layout design. Collaborating effectively with in-house and client team members. Developing accurate layout design schedules and resource estimates. Proactively looking for continuous improvement opportunities in the flow, layout and design methodologies.

Challenges: Adapting to, and implementing frequently changing Design rules. Quickly getting aquatinted and fluent with different fab technology. 3nm/5nm Finfet [Nov 20-Sep 22]

As a contractor through IC enable, worked in multiple projects ranging from individual blocks up to top cell level under various domains like: Full custom digital, mix signal, analog. Responsibility: Efficient floor planning, critical signal routing, Track sharing Producing DRC and LVS clean layout.

Taking particular care of process variations and deep sub-micron effects. To Create a strong power network.

Fixing DRC and LVS of a pre-done layout.

To maintain continuous communication with the circuit design team. Challenges: To get fluent in use of new technology within a short period of time. Efficiently solving intricate DRC and LVS errors.

IBM RF 90nm [Aug 19- May 20]

Project: Full Duplex Communication for Wireless Network on Chip Responsibility: Full planning and execution of the project Worked on circuit design, and spice simulations followed by floor-planning, placement, and routing. Delivered on time with best quality of layout. Published paper in IEEE. Challenges: Achieving desired simulation results (interference isolation in db). Efficient DRC and LVS cleaning.

Area efficient and tight schedule to meet.

16nm TSMC Finfet [Nov 18 - Jan 19]

Project: Bias block giving reference current to all other sub-blocks of module Responsibility: Current mirror block, reference block, Interdigitation matching for current mirrors.

Taking care of process variations and deep sub-micron effects LOD, WPE. EMIR calculation for the output current routing.

Challenges: Ramp Up of new technology within a short period of time Efficiently solving DRC errors Efficiently

fixing antenna errors.

28nm TSMC

Project: LDO Low drop Output 1.2v (derived from 1.8v supply) Responsibility: Complete ownership of floor planning, routing, verification and sign-off. Closely work with the designer to meet the specification requirement. Worked on all sub-blocks like resistor divider, diff-amp Meet EMIR constraint requirement for output bumps

Base and Metal density fill closure inclusive of min and max density Antenna, ESD and Latch up sign-off.

Challenges: Design updates were implemented quickly with in layout tight schedule was met with best quality of layout.

180nm UMC

Project: Analog building blocks

Responsibility: Worked on Diff amp, comparators, DAC, BGR Area estimation and planning

Matching diff-pair and symmetrical routing pairs to avoid mismatch Shielding critical signals to avoid noise coupling.

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