Graduate Engineer

Rafat Enam

619-***-**** / *********@*******.***

**** ******* ****** ******, ** 92780

WORK AUTHORIZATION

Legally authorized to work with any employer in USA without requiring sponsorship. OBJECTIVE

Looking for a full time opportunity as an Engineer where I can unfold my technical expertise and problem solving skills to test and certify wide variety of electro-medical devices.

EDUCATION

San Diego State University, Master of Science (MS) in Electrical Engineering (Fall 2013 – and Fall 2016)

Sathyabama University, Chennai, Bachelor of Engineering in Electronic and Instrumentation Engineering. (2008 – 2012)

SKILLS

Programming language: Verilog HDL, Matlab, C programming. Hardware Simulator: Cadence (CAD tool) Virtuoso, Mentor graphics IC station, Xilinx ISE, Layout XL, Comsol, Coventor, PSpice, Agilent ADS, Xilinx, Matlab, LabVIEW, Simulink, Agilent ADS, EDA, PCB layout, FPGA.

Operating System: Linux, Windows, Ubuntu, Android, Microsoft (Word Excel, PowerPoint) Instrument and Lab Equipment Handled: Sensors (Current, voltage, power, flow, speed and temperature), Power supply system (AC/DC), Signal Analyzers, Multimeter, Analog Device and Oscilloscope.

COURSES

MEMS: Design rule and Finite Element Analysis (FEA) of MEMS using COMSOL and Coventor.

ASIC Design: Booth encoded Wallace tree multiplier using cadence. Adaptive Algorithm: FIR filter Equalizer Canceler by Adaptive Algorithm, DFT and FFT analysis using Matlab

Microwave Sys Theory: RF circuit design and Matching of single and double stub tuning using Agilent EDA Tool.

Digital Signal Processing: High frequency noise filtration of Low pass, High pass and Band Reject filter using Matlab.

ACADEMIC PROJECTS

Studied various Biomedical Devices

Hands on experience in biomedical instrument such as electrode, transducer and imaging system. Validated and verified various biomedical device such as EEG, EMG, ECG, Pacemaker, Defibrillators and stethoscope.

Design of Low Power High Performance Booth Encoded Wallace Tree Multiplier Design of Sub-system such as Booth encoder, Partial Product Generator, Full adder, half adder in transistor level using adiabatic designs. Performed Transient analysis to calculate the delay and power consumption and then Mixed signal analysis is performed on the design for functional verification.

Schematic of transistor level Circuit Design

Designed High performance adder and multiplier architectures module technology using IC layout, NAND, NOR, XOR, Inverter, CMOS, CPL, TG and Domino logic gate via Cadence tool in optimized power, speed and voltage regulation.

Design Micro-Electromechanical System (mems) using EDA tool Designed annular ring antenna using coventorware and then fabricated the mask via positive photoresist technique to obtained highly customized chip. Gained experience on positive and negative lithography.

FIR Equalizer and canceler

Designed and implemented a 40 Tap FIR Filter equalizer and canceller using decision directed LMS and RLS algorithms using Matlab. Determined I/O response of channel Error Correction with Learning curve, Eye Diagram and Constellation. WORK EXPERIENCE

Student Research Assistant at San Diego State University AUG 2015 – DEC 2015 Tested, debugged and verified mixed signal design using Cadence tool. Tested and verified Radio detection and ranging (Radar) used in traffic signal control. Working as a team player helped me meeting the project deadlines and learn time-management skills.

Publishing my Master’s Thesis report globally has equipped me with the skill to reach my work to the outside world in an effective manner and also helped me gain strong communication and interpersonal skills.

THESIS EXPERIENCE

Designed and implemented an efficient linear phase digital filter using MATLAB. I have used DFM and DMR technique to design Digital Filter. The steps involved executing and analyzing the impulse and frequency responses by combining polyphase low pass FIR and IIR filters. This was achieved by calculating the necessary workload analytically in every step to conclude how multiple stage implementation can reduce the workload considerably with a gradual increase in signal delay.

Contact this candidate