NAWRIN I. NATASHA

Arlington, TX ***** 469-***-**** aczqzg@r.postjobfree.com https://www.linkedin.com/in/nawrin-natasha EDUCATION

University of Texas at Arlington, Arlington, TX May 2017 Master of Science in Electrical Engineering GPA: 3.67 Coursework: Embedded Microcontroller Systems, Microprocessor Systems, Digital/Analog CMOS IC Design, Semiconductor Device Theory, IC Fabrication, MEMS

North South University, Dhaka, Bangladesh May 2014 Bachelor of Science in Electrical and Electronic Engineering GPA: 3.75 Coursework: Verilog HDL, VLSI Chip Design

TECHNICAL SKILLS

Prog. Language: Verilog, VHDL, C, C++, Embedded C, RISC, x86, JAVA, Perl, Python Tools: PLC, Cadence Virtuoso, Pspice, AutoCAD, Revit, MATLAB, Modelsim, Xilinx ISE, SKM,PSIM Architectures: x86, RISC, Intel 8085, Intel 8086, ARM Cortex-M4 Protocols: SPI, UART, TCP/IP, HTTP, DMX-512, I2C

Electrical Testing Tools: Function generator, Oscilloscope, Network Analyzer, DMM Others: PCB layout, Altium, Microsoft Word, Excel, PowerPoint EXPERIENCE

System Engineer Intern Grameenphone Ltd. May 2016–Aug 2016

• Built 3 PAT reports on operation and maintenance of Base Transceiver Station(BTS) and optical fiber network.

• Investigated the working condition of BTS and reported to supervisor if issues found. Embedded System Engineer Aplombtech BD Bangladesh May 2014-Aug 2015

• 32-bit RISC microprocessor design -- Designed 32-bit microprocessor based on Harvard architecture with 4-stage pipeline (IF, RR/ADDGEN, FO/EX, WB). It included data memory interfaces, ALU, and the pipeline control logic with full resolution of structural, control, and data hazards.

• Cache Controller Architecture – Developed C code to determine the best architecture for a cache controller that interfaces with 32-bit microprocessor with 32-bit data bus. Used fast Fourier transform routine to determine the lowest average memory access time required by different combination of associative set size, burst length, write strategy and replacement strategy.

Research Assistant Independent University Bangladesh May 2014–Apr 2015

• Successfully designed an efficient way to track the maximum power point in a photovoltaic inverter by Incremental Conductance algorithm. http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7026943&isnumber=7026810 Laboratory Instructor North South University Bangladesh May 2013–Apr 2014

• Conducted lab sessions for C programming, AC circuits, DC circuits and Digital logic devices.

• Achieved more effective way to teach C programming and improved class performance by 40%. PROJECTS

Fabrication of MOS Capacitor in class 100 cleanroom.

• Performed FEOL semiconductor process flow in nanofab cleanroom that includes RCA cleaning, thermal oxidation, spin coating, diffusion, photolithography, metal deposition, developing, etching.

• Extracted the coefficients for the Deal-Grove oxide growth equation. SDRAM Controller Design

• Designed a controller that allows the memory (MT48LC8M8A2) to be interfaced with a microprocessor (80386DX) having asynchronous memory support.

• Full solutions of state machine and bank signal generation with data masking, data flow, ready logic and refresh support DMX-512A protocol implemented on Cortex M4F series ARM controller

• Developed C code for 32-bit ARM Cortex-M4 CPU using TM4C123GXL microcontroller to build a controller for a time intensive asynchronous communications interface based on DMX512-A protocol with EF1 topology.

• PC transmitter accepted commands via RS-232 interface and controlled 512 devices on a RS-485 communication bus.