Vinod Chandrasekar

****, **** **** ******, *** **0, CO-80521 970-***-**** acznuy@r.postjobfree.com

https://in.linkedin.com/pub/vinod-chandrasekar/76/10/571 Education

Colorado State University, CO CGPA-3.2

MS Electrical and Computer Engineering, (Expected - May 2017) Sri Krishna College of Engineering and Technology, Coimbatore, Tamilnadu, India CGPA-8.0/10 BE Electronics and Communication Engineering (May 2013) Coursework

ECE 561- Hardware and Software design of embedded systems, ECE 451- Digital System Design, ECE 571- VLSI system design, ECEN 5593- Advanced Computer Architecture (UC Boulder) Experience

Graduate Intern - Robert Bosch LLC, Farmington Hills, Michigan, USA GM C4B: (May, 2016 to August, 2016)

Automated test scripts using python and CAPL so that the communication between Center Stack Module(CSM) and the instrument cluster (GM, Chevrolet cars and trucks), can be performed without any manual effort.

Set up a comprehensive hardware test bench that ensured a full-fledged cluster setup having proper communication between the cluster, the CSM (Ethernet) and the steering wheel control (LIN).

Setup Ethernet flashing and CAN flashing and also performed MULTI debugging. Associate Software Engineer - Robert Bosch Engineering and Business solutions, Coimbatore, India BMW L6 FPK: (February, 2014 to June, 2015)

Developed an AUTOSAR compatible embedded software for BMW variant cars (5 and 7 series) and specialized in the service layer of the AUTOSAR model for Model Years 2015 and 2016

Updated calibration parameters, integrated HMI and Check control DB.

Configured Diagnostic Trouble Codes and held responsibility for overall diagnostics module.

Performed enhancements and bug fixes in Vehicle processor subsystem (32 bit Fujitsu processor, OSEK OS), Graphics processor subsystem (64 bit Capricorn processor, Vxworks OS) and APIX supported Head Up Display systems using embedded C following MISRA standards. Skill Set

Programming Languages: C, C++, Python, Embedded C, CUDA, VHDL, Verilog, Java, SystemC. Tools/ IDE: Eclipse, NetBeans, Altera Quartus, Cadence Virtuoso, Windriver, Noxim, RTC, Clearcase, Clearquest, PIN tool, GEM5, DOORS, MATLAB, TRESOS, Tornado, CANOE, Xilinx, MULTI, CAPL, Altium, Eagle, Mercurial. Protocols: CAN, MOST, I2C, UART, APIX, Ethernet.

OS: Linux, Vxworks, OSEK, FreeRTOS.

Academic Projects

Parallelizing K-means algorithm for Image clustering (May, 2016 – August, 2016) Parallelised K-means algorithm, where images are clustered based on centroids, using CUDA. 8-bit synchronous counter (February 2016 to May, 2016) Implemented an 8-bit synchronous counter in Cadence Virtuoso in schematic first and followed it up with an implementation of the layout using Encounter tool. Performed DRC, LVS and QRC on the layout. Branch Predictor Implementation using PIN tool (February, 2016) Implemented a hybrid branch predictor using Intel’s PIN tool and obtained a prediction accuracy of 94%. Traffic Light Controller- Finite State Machine (November, 2015) Implemented a Traffic light control system, performing state reduction using implication chart, in Cadence and developed the Verilog code for the same and executed it in the Altera Quartus board. Logarithmic Multiplier (October, 2015)

Implemented a Logarithmic multiplier in Cadence using a Log ROM look up table and implemented the same in Verilog and executed in Altera Quartus FPGA board. 16x8 SRAM cache (September, 2015 – October, 2015)

A two-level addressing algorithm was developed to reduce the complexity of control logic for address decoder using System C.

Training

Underwent project training on the development process of SMD PCBs at Samsung Electronics India Limited during the month of December, 2012.

Programmer Analyst Trainee at Cognizant Technology Solutions from December, 2013 to February, 2014 and was trained in Java, SQL and C.