Mechanical Engineer Design

Harvey Tran

El Dorado Hills, CA ● **************@*****.*** ● https://www.linkedin.com/in/harveytran ● 916-***-****

Dedicated and accomplished Thermal / Mechanical Engineer / IC package design / Quality and Reliability, and Engineering leadership, offering over 19 years of experience in the semiconductor industry. Proven leader with the ability to manage teams, deliver projects on aggressive schedules, and have exceptional problem solving skills. Additional core competencies include:

Proven knowledge of Mechanical simulation, Thermal simulation, and data correlation ● Statistical analysis ● GD&T ● IC Package design, interposer design, and PCB design ● Designed from concept to Production Phase ● Team Leadership ● Suppliers Management ● Risk Assessment and Remediation ● Developed Qualification test plan ● Exceptional Verbal and Written Communication Skills.

Career History

Intel Corporation Jun 1997 to Nov 2016

Platform Quality & Reliability Engineer (2013-2016): Owned qualifying and releasing Intel’s phone and tablet development platforms. Assessed HW and SW risks in the platform and created Platform Quality and Reliability Validation (PQRV) test plans to mitigate platform risks. Performed Highly Accelerated Life Test (HALT) and Mean Time Between Failure (MTBF) tests per the PQRV plan and drove for fixes if ingredients did not meet Quality and Reliability (Q&R) targets. Analyzed Q&R and validation test data to assess health of platforms for each platform’s milestone (Alpha, Beta, PLQ). Documented platform risks in the Platform Quality and Reliability Release Criteria (PQRC) and presented to stakeholders, senior leaders, and made a final recommendation on platform’s milestone declaration.

●Recommended action on whether or not to declare platform’s milestone based on Q&R and validation test results.

●Collaborated with many cross-functional teams to address HW & SW risks in the platform and developed PQRV test plan to eliminate risks to launch the platform.

Mobile Thermal/Mechanical Development lead (2009-2013): Led a team to deliver test sockets with an integrated thermal solution for silicon and system validations. Also, owned developing and delivering an enclosed chassis designs for phone’s development from prototype through production phase. Built 3D models and ran mechanical simulations to verify designs are robust prior for prototype builds. Created characterization test plan to verify designs met mechanical, thermal, and electrical requirements before releasing designs to High Volume Manufacture (HVM). Managed suppliers’ and ODMs relationships from prototypes to high volume builds. Managed test resource, budget planning, and scheduling for all projects.

●Delivered innovative test sockets solution with an integrated thermal solution for silicon and system validation.

●Realized cost savings of millions of dollars by creating a simple and user friendly test socket HW solution.

●Delivered enclosed chassis designs for phone’s development for show case in the Mobile World Conference (MWC).

IC Package Design lead (2006-2009): Led a IC package design team to deliver Wire-Bond (WB) and Flip-Chip (FC) packages to support Microprocessor, Networking, and Embedded devices. Made IC packages recommendations to customers based on thermal, mechanical, electrical, reliability, and cost target requirements. Supported package routing feasibility study from die to package and to board. Gathered design requirements, and assured package thermal, mechanical, and electrical requirements were properly implemented into the physical layout. Utilized Cadence Advance Package Design (APD) tool for layout. Managed the substrate vendors’ relationship and owned driving substrate manufacturing design rules and assembly rules to support product’s road-map. Chaired package design review sessions with stakeholders for achieving package tapeout approval. Owned signing off on designs, its collaterals, and releasing them into design database.

Chaired Package Design Work Group to drive package design / assembly rules to support products roadmap.

●Managed group resource, mentored, and trained team members on designing WB and FC packages.

●Consistently taped-out packages on schedule and always delivered first article in time for silicon validation.

●Collaborated with SW automation team to develop Package Layout Automation (PLA) tool to improve design TPT.

IC Package Mechanical Engineer (2003-2006): Supported customers on shock testing to prove Intel products are robust during shipping and handling. Worked with customers on test plan, defined pass/fail criteria, and schedule requirements. Constructed Ansys model and ran simulation. Built test board and test package based on JEDEC standards and performed shock testing. Correlated test data with simulation model. Performed dye and peel analysis on test units, created test reports, and presented to customers.

●Worked closely with customers on test requirements and scheduling needs.

●Consistently delighting customers by delivering test results on a timely manner.

Earlier Roles at Intel: IC Package Thermal Engineer (2000-2003), IC Package Design Engineer (1997-2000)

Professional Training

Bachelor of Science, Mechanical Engineering, Rochester Institute of Technology (RIT)

Technical Proficiency

PTC Creo, SolidWorks, Flotherm, Ansys, AutoCAD, Mechanica, Cadence Allegro, Avanti Package Design

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