Electrical Engineering Design Engineer

GE (GRACE) YU

Phone: 604-***-****

Cell phone: 604-***-****

E-mail: aczkpz@r.postjobfree.com

HIGHLIGHTS

• Specialize in high-speed transistor-level Analog/Mixed-Signal IC design (especially for high speed and high performance PLLs which include LC-VCO, PFD/Charge- pump, programmable dividers and related circuits), development, layout, and verification for CMOS circuits (such as TSMC 90nm, 65nm,40nm, etc.)

• Proficient in various IC CAD tools such as Cadence Spectre and Cadence Virtuoso

• Excellent knowledge of Calibre, Assura, and analog layout (including DRC, LVS, and RC extraction)

• Four tape-outs (two 90nm and two 65nm)

• Familiar with lab tools such as oscilloscope, power supply, spectrum analyzer, soldering equipment, etc.

• Excellent communication and team work skills

WORK EXPERIENCE

August 2016 – March 2017 Analog IC Design Engineer, Appotech Canada Inc. (Analog team in Canada dissolved due to shortage of work)

6GHz Phase-Locked Loop for Serial ATA project (using 40nm technology)

• Designed and simulated (including PVT simulations) a dynamic divide-by-2 divider and a programmable CMOS multi-modulus divider (divide-by-5 to-127).

• Designed and simulated a phase frequency detector with delay selections and a single-ended charge pump with op-amp.

Jan 2010–July 2016 Research Assistant, System-on-Chip Group, ECE Dept, University of British Columbia (UBC)

20GHz Phase-Locked Loop (using TSMC 65nm technology)

• Differential LC-VCO designed, laid out (which includes DRC, LVS, and RC extraction), verified post-layout simulations, and fabricated; this VCO has a phase noise of -114dBc/Hz at 1MHz offset and a tuning range of 16GHz-23GHz.

• Divider (including high speed CML divider and CMOS divide-by-32-to-63 multi- modulus divider) designed, laid out, verified post-layout simulations, and fabricated.

• Designed and simulated the phase frequency detector, differential charge pump with op-amp, and differential loop filter. Simulated the closed-loop PLL with all real circuits as well as circuits combined with Verilog-A to speed up simulation time. 5GHz LC-VCO and 10GHz LC-VCO (designed and simulated using TSMC 65nm) Two Wideband CMOS 13-GHz LC-VCOs (using TSMC 90nm technology)

• LC-VCOs designed, laid out, verified post-layout simulations, and fabricated.

• Designed a biasing circuitry, charge pump, PFD, and loop filter; simulated closed- loop PLL using Verilog-A divider combined with other real circuits.

• Successfully tested the chips using probes.

2012 – 2014 Teaching Assistant, ECE Dept, UBC

• Courses: EECE 251 (Circuit Analysis I), EECE 253 (Circuit Analysis II), EECE 450

(Engineering Economics), APSC 540 (Business Decisions for Engineering Ventures)

• Responsibilities: Conducting lectures, Designing teaching materials, Grading. EDUCATION

Sept 2012 –July 2016 PhD Candidate, Electrical Engineering, GPA 4.33/4.33, UBC Concentration: Analog and Mixed Signal Integrated Circuit Design Thesis: Design and Analysis of Low-phase-noise Wide-tuning-range Multi-GHz Phase-locked Loops (20GHz PLL using TSMC 65nm technology); completed the course requirement and the majority of the research work. Jan 2010–Oct 2012 MASc, Electrical Engineering, GPA 4.3/4.33, UBC Thesis: A Study of Two Wideband CMOS LC-VCO Structures

(13 GHz PLL using TSMC 90nm technology)

Sept 2004–Dec 2009 BASc, Electrical Engineering, with Distinction, UBC VOLUNTEER EXPERIENCE

2011–2014 Student Ambassador for UBC ECE Department SKILLS

Computer Skills

• Tools, Languages, and Software:

o Familiar with Cadence Spectre and Virtuoso, Matlab, and Microsoft Office. o Knowledge of Hspice, Verilog, VHDL, Altium, C, and C++.

• Operating Systems: Windows, Unix

Language

• Fluent (native proficiency) in English and Mandarin Chinese AWARDS

• 2004 Charles and Jane Banks Entrance Scholarship SELECTED PUBLICATIONS

“Verifying Global Convergence for a Digital Phase-Locked Loop,” Ge Yu, Jijie Wei, Yan Peng, and Mark Greenstreet, in Formal Methods in Computer-Aided Design, 2013.

“Performance Comparison of Two Wide-Tuning-Range 13-GHz CMOS LC-VCOs”, Ge Yu, Shahriar Mirabbasi, and Andre Ivanov, in IEEE International Conference on Electronics Circuits and Systems, 2014.

CITIZENSHIP: Canadian

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