Technical Management, Product Management, Design Engineer, Development

Anurag Sharma 1-973-***-**** aczdfx@r.postjobfree.com linkedin.com/in/asharma-us

25+ years of technical management and product development experience in delivering complex large-scale enterprise systems and solutions. Leadership roles in wireless industry with proven track record of producing quality results through building efficient, high performance, cross- functional and global R&D teams with sharp focus on delivery efficiency and execution. PROFESSIONAL EXPERIENCE

Nokia, Mobile Networks, Murray Hill, NJ

Small Cells Product Management Leader (Advanced Tech & Architecture) 09/2016 – Present

Responsible for driving advanced technology initiatives for the femto cell products within the Small Cells organization for the residential, SOHO and enterprise market. End-to-end program management of new products by formulating product requirements, defining roadmap and proposing technical solutions to meet program cost and schedule commitments. Active involvement in partner/supplier management to negotiate requirements, intellectual property agreements, and pricing, in alignment with customer acceptance criteria, risk/opportunity analysis and overall business development strategy.

Provide strategic direction and technical analysis for the business development of forward looking initiatives in areas such as, 5G, IoT, virtualization (SDN/NFV), cloud and hosting solutions (SCaaS) for the indoor femto cell products. Define features and use cases in diverse areas, including but not limited to MEC, NBIoT, IoT gateways, CAT-M, LoRA/LPWAN, M2M communication, Multefire, LAA, etc.

Evaluation of customer requests and requirements definition for new products in LTE licensed/unlicensed bands including up and coming spectrum allocations, e.g. CBRS 3.5GHz shared spectrum, 600MHz etc.

Analyze and provide recommendations for overall indoor femto cell product architecture, including hardware (SoC, chipsets), software (LTE stack, OAM, applications) and security solutions. Nokia (formerly Alcatel-Lucent), Mobile Networks, Murray Hill, NJ Global Software Director, RF R&D 02/2015 – 08/2016

Functional leadership of a global SW development organization. Responsible for managing all aspects of full SW lifecycle for about 100 radio products with a worldwide deployed base of about a million units.

Provide strategic and technical direction to a global team of 100+ engineers in the US, China and the UK.

Oversaw significant growth of the SW team while continuously improving on quality benchmarks and KPIs, such as 20% improvement in customer responsiveness and eliminating autonomous resets from radio code.

Ownership and responsibility of SW feature development for new and existing radio products.

Establish infrastructures, processes, development tools and SW development guidelines for global ALU radio product portfolio. Drive process compliance initiatives and ensure commonality across products.

Successful introduction of a common HW asset platform and DAS (Distributed Antenna System) interface in service provider networks to lower costs and expand mobile ultra-broadband access in public locations.

Resource management duties with focus on cultivating people career development. Alcatel-Lucent, DECP, Multi-standard Assets & Platforms, Wireless Division, Murray Hill, NJ SW Development Manager & Technical Project Lead – LTE BBU Platform 03/2011 – 01/2015

Responsible for setting technical direction for a large cross-location global team of 120 engineers in the US, France and China; and delivering BBU platform software for Alcatel-Lucent's 4G Wireless Systems.

Responsible for the successful introduction of a new baseband controller board that served as a key component in delivering 6x capacity improvements in ALU’s LTE offerings. This project required active management of a global, multi-disciplinary team comprising all aspects of a new product introduction involving HW/SW design, system architecture, capacity analysis, supply chain, advanced procurement, production, budgeting, models management, multi-domain verification/integration, compliance testing etc.

Significantly improved code quality and performance benchmarks, such as speeding board bring up by 7x, reducing code complexity indicators by 5x, enhancing code coverage by 40% and automation of test code.

Managed end-to-end software development lifecycle including estimation, commitment, architecture, design, development, unit test, feature verification, delivery and sustaining/maintenance/EOL activities. Team Lead/DPM, Release Manager – LTE BBU Platform 06/2004 – 02/2011

Responsible for overall BBU platform SW feature deliveries into all ALU LTE releases.

Led an engineering team to develop resource objects (ROs) signifying Hardware Resource Abstraction Layer (HRAL) components that were responsible for administrating eNodeB’s control, baseband and RF resources under the direct supervision of OAM-C. Subject matter expert for HRAL layer, base classes and common framework implemented in C++ to manage embedded SW objects in a distributed system.

Developed first versions of all resource objects in accordance with the HRAL framework for multiple controller/modem boards, including host functionality for these objects to relieve hardware dependencies.

ScrumMaster and team mentor for two BBU platform pilot projects under the Agile software development methodology. Actively coordinated with Product Owners in managing the product backlog and burndown. Managed daily sprint activities, resolved blocking issues and delivered sprint output to main load line. Software Architect (3GPP UMTS System on a Chip Project) 11/2000-06/2004 Established an architectural framework for a verification model that simulated an entire ASIC in software to aid bit-exact verification. Designed and implemented an extremely flexible and efficient multi-format data translation engine capable of generating single and multiplexed output streams for all simulation data. This approach provided the ability to debug the entire code base either vertically or horizontally by inheriting debugging traits at run time via XML input and yielded 25x performance gain. SCO Inc., Unix System Laboratories (USL), Murray Hill, NJ Technical Lead (Core OS development) 02/1996-11/2000 Responsible for the design, implementation, delivery and maintenance of the UDI hotplug infrastructure, PCI hotplug and Compact PCI hotswap solutions in UnixWare. Ownership of the overall hotplug/hotswap framework. Conducted technical demos, consulted and liaised with IHVs to develop their hotplug and hotswap solutions. Participated in various special interest group (SIG) initiatives and industry standardization efforts. Novell Inc., Unix System Laboratories (USL), Florham Park, NJ Software Development Consultant 09/1994-02/1996

Designed and developed custom engineering solutions involving complex system configuration scenarios in heterogeneous environments (UnixWare, Sun Solaris and IBM AIX). Customized performance tuning of enhanced UnixWare command base around the fault resilient Amadeus OS-based on the Chorus microkernel. Oracle Corporation, Redwood Shores, CA

Software Development Consultant 03/1994-09/1994

Responsibilities included the implementation and maintenance of a shared memory-based protocol between a massively parallel Supercomputer and a Pentium-based Single Board Computer running the multiprocessing version of Novell UnixWare (4.2MP) for a prototype Video on Demand service. Design, development and maintenance of a PCMCIA Host Bus Adapter driver and its interface to the SCSI Device Interface. Summit Design Inc., Beaverton, OR

Software Design Engineer 06/1993-03/1994

Responsibilities included the design and implementation of simulation data translators that automatically generated verification code for Automatic Test Equipment (ATE) systems utilizing standard/proprietary APIs. Synopsys Inc., Logic Modeling Division, Beaverton, OR Software Design Engineer 01/1990-06/1993

Responsibilities included specification and implementation of a standard SW API between the SmartModel library and various Electronic Design Automation (EDA) simulators. Created an efficient stimulus-response format to record the interaction between models and simulator nets. Designed and implemented behavioral simulation models for complex digital integrated circuits, utilizing a proprietary modeling language. QUALIFICATIONS AND TECHNICAL SKILLS/EXPERTISE

Education: M.S. Computer Science, New Jersey Institute of Technology, Newark, NJ Languages/Env: C++, C, Java, Python, XML, html, TCL, Perl, Lisp, IA Assembly, Linux, VxWorks, Jira Methodologies: Design Patterns, OOP/D, UML, DevOps, Lean/Agile (Scrum), (A)TDD

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