Engineer Electrical Engineering

Pallavi Dulloo

https://www.linkedin.com/in/pdulloo

*******.******@*****.*** +1-312-***-****

Hardware Engineer with a good academic background and professional experience in VLSI. Worked on functional and physical verification techniques, and ready to take up challenges with the latest technology trends. Dedicated and enthusiastic about all the tasks assigned.

EDUCATION

Master of Science- Electrical Engineering, Illinois Institute of Technology, Chicago December 2016 Concentration – Computers and Microelectronics, GPA - 3.81 Bachelor of Technology- Electronics & Communication Engineering June 2011 Madan Mohan Malaviya Engineering College- UPTU, India WORK EXPERIENCE

Project Engineer at WIPRO Ltd., Bangalore, India July 2011- October 2014

• DESIGN VERIFICATION ENGINEER

Client- Internal Duration- 3 months

Analyzed the Design Specification Document provided for the components in an internal project. Created Verification Document and coded test cases in Specman.

• DESIGN VERIFICATION ENGINEER

Client- Intel Corp. Duration- 10 months Technology- 28nm Functional verification on a project for the camera sub-system of a mobile phone. Handled complete modules and did Random Test Generation in Specman. System-on-Chip Verification in ERM Technology on functional blocks using Incisive Simulator and Specman Elite, and Simvision Waveform Viewer.

• PHYSICAL VERIFICATION ENGINEER

Client- Intel Corp. Duration- 9 months Technology- 14nm Worked as a Mask Designer on a project for Physical Design Verification (PV) of Functional Unit Blocks. Performed PV checks (DRC/LVS/ERC) on individual unit blocks using IC Validator and Hercules and Intel’s internal design flow.

TRAININGS

WIPRO Technologies, Bangalore, India August - November 2011

• Attended training on Design for Testability. Tested designs for synthesis and the fault patterns generated using Synopsys DFT Complier. Performed linting, and formal verification using SpyGlass Lint.

• Underwent Specman training by Cadence faculty. Created a Verification Environment for testing Router designs.

ACADEMIC PROJECTS

• Illinois Institute of Technology, Chicago January - April 2016: Designed multi-gate field effect (FinFET) transistors (45nm) in various modes to compares their characteristics and performance using HSPICE simulations and Synopsys Cosmoscope.

• Illinois Institute of Technology, Chicago January - April 2016: Simulated a data path of CPU, cache, bus and memory for a 32-bit version of MIPS processor to understand the function of the architecture in VHDL. Created the architecture of all modules and verified with number of instruction sets for complete processing using ModelSim.

• Illinois Institute of Technology, Chicago January - April 2015: Designed and Synthesized various Carry Propagation Adders with datapath circuit design in Verilog using Synopsys Design Compiler. Performed standard cell based design flow in 45 nm technology, and design validation and verification through construction of fast adder architectures using Cadence Virtuoso and Encounter, Mentor Graphics Calibre and Synopsys Formailty ESP.

• Indian Institute of Technology, Delhi June - July 2010: Undertook a summer internship program at the Centre of Applied Research in Electronics about the design of Patch Antennas at microwave frequency.

• Madan Mohan Malaviya Engineering College January - May 2011: Designed and Simulated Triple Band, Double-U Slot Patch Antenna for WiMAX Application. TECHNICAL SKILLS

Programming Languages : Verilog, Specman, HSPICE, C/C++ Platforms : Windows, Linux, OS X

CO-CURRICULAR ACTIVITIES

• Secretary of the IEEE Student Branch, Madan Mohan Malaviya Engineering College in 2010-2011.

• Membership Development Officer of the IEEE Student Branch, Madan Mohan Malaviya Engineering College in 2009-2010.

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