ROHIT MISHRA

Gainesville, FL ***** • 352-***-**** • aczc34@r.postjobfree.com • linkedin.com/in/rohit-mishra-b5864376• github.com/rhtmishra2013

OBJECTIVE

Electrical & Computer Engineering Graduate with two years of professional Work Experience in Software Development & Scripting and one year of research experience in Design & Optimization of Applications on Field Programmable Gate Arrays seeking the role seeking Computer Software position.

EDUCATION

Master of Science in Electrical & Computer Engineering (Current GPA – 3.44/4.00) May 2017

University of Florida (UF), Gainesville, Florida, USA

Coursework: Reconfigurable Computing Computer Architecture VLSI Virtual Computers Embedded Systems Advance

Systems Programming Digital Image Processing Hardware Security Lab Pattern Recognition

Bachelor of Engineering in Instrumentation & Control Engineering (GPA – 8.55/10.00) May 2013

SRM University, Chennai, India

Coursework: Microprocessor and Microcontrollers Design Project Lab Virtual Instrumentation Robotics and

Automation Neural Network and Fuzzy Logic Signal Processing and Telemetry Digital Design Linear Integrated Circuit

EMPLOYMENT

Graduate Research Assistant – NSF Center for High Performance Reconfigurable Computing (CHREC), UF (Gainesville, USA)

Wrote a Guideline on usage of Novo-G a Reconfigurable Supercomputer. Aug 2016 – Jan 2017

Designed a RTL/Hardware wrapper around the LBM PE in Verilog for fast Data Streaming through PCI-e and timing Closure.

Implemented an OpenCL framework for scaling the LBM Application across two Stratix V FPGA’s.

Designed and Implemented RTL Verification Testbenches for 35,000 lines of Synthesized Verilog Code.

Optimized the Existing LBM Processing Element design and achieved an 18% reduction in resource utilization on Stratix V.

Achieved a Peak Performance of 18.5 GF/s.

Assistant Systems Engineer – Tata Consultancy Services (New Delhi, India) July 2013 – July 2015

Supervised a team of two developers involved in reverse Engineering phase for Requirement Gathering and Analysis from the Client.

Executed regression and functional testing of the application using Bash Scripts to ensure proper implementation of Change Request and Enhancements before deploying to Production system.

MVC architecture based model was developed using C++ in the front end and SQL (Pro-c*) in the back end for database manipulations.

UML Modelling and Testing using Bugzilla.

ACADEMIC PROJECTS

SMS spam detection using Machine Learning – University of Florida (Gainesville, USA): Jan 2017 - Mar 2017

Designed a Supervised Machine Learning Model for detection of spam messages using Python and Scikit-Learn.

Implemented SVM method, KNN Classifier and Naïve Bayes Classifier for training the model.

Achieved an accuracy of 96% using Naïve Bayes Classifier.

Augmented Reality based Weather Station Application– University of Florida (Gainesville, USA): Aug 2016- Dec 2016

Designed an Application that Augmented Weather data on Hand held Devices using OpenGL.

Implemented an Image Processing Algorithm using OpenCV and Java.

Achieved a dual mode communication between multiple Hardware devices (Arduino) and software (Java) using serial port.

Multiple Mode Linux USB Keyboard Driver– University of Florida (Gainesville, USA): Jan 2016- April 2016

Modified the Linux USB Keyboard device Driver code for supporting two different modes.

Designed & optimized data structures in C for handling the requests from the Keyboard efficiently.

Dynamic Cache Replacement Policy– University of Florida (Gainesville, USA): Aug 2015- Dec 2015

Modelled a new Cache Replacement policy based on recency.

Improved the Cache Performance by 6% against the classical LRU Algorithm on Simplescalar.

Implemented Machine Learning for training the Cache Algorithm.

Perform Hardware Attacks on a Hardware Hacking Board – University of Florida (Gainesville, USA): Aug 2016 - Dec 2016

Implemented an 128 bit AES encryption on a custom PCB board powered with Max 10 FPGA board using Verilog

Designed and implemented a Clock Glitch attack using Verilog to produce bit faults.

Implemented a DFA on an AES and wrote a MATLAB script to make the guessing procedure faster.

1D Time-Domain Convolution on Xilinx Zynq Board– University of Florida (Gainesville, USA): Aug 2015- Dec 2015

Designed a pipelined datapath and memory controller for the convolution using VHDL.

Used CDC techniques to synchronize memory running at 100 MHz and Logic Clock running at 166 MHz.

Achieved a throughput of 1.3x compared to CPU.

TECHNICAL SKILLS

Programming Languages and Platform: VHDL, Verilog, Tcl, C, C++, Python, MATLAB, OpenCL, Linux Kernel Programming, Bash, LabVIEW, Processing 3.0, C#, DBL, Java, VB.Net, SQL, JTAG Debugging, MS Visual Studio, Networking, Virtualization

Design Tools: Quartus, Vivado, Modelsim, Cadence,SPICE, SignalTap, Keil Microvision 4, Atmel Studio 7, Simplescalar, KVM.

Hardware Platforms: Stratix IV, Stratix V, Zynq 7020, Max 10, Cyclone V, Atmel AVR, Arduino.

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