Physical Design Engineer
Resume:
Jason Hu
Senior Physical Design Engineer
San Jose, CA 95131
E: ***********@*****.***
Jason Hu
Senior Physical Design Engineer
OBJECTIVE
I’m looking to work as a physical design engineer who will do the auto P&R, from floorplanning to tapeout for chip design field.
SUMMARY
I’ve been working in layout / auto P&R field for almost 18 years and with strong background on the back-end side. I’ve also been working on timing driven P&R for the last 10 years. EXPERIENCE
Physical Design Engineer (Layout Designer), Level One Communications, Inc. / Intel, Inc., March 1996 - September 10, 1999
C ustom Layout Design, from floorplanning to tapeout, including stdcell layout, using Cadence layout tool Auto P&R, from floorplanning to tapeout (including LVS/DRC fixes), block-level / chip-level, using Astro. Accomplishments
● Fully custom design stdcell cell layout library set.
● Auto P&R, from floorplanning to tapeout (including LVS/DRC debugging / fixes), block-level / chip-level, using Astro.
● Multi-tasking - doing multiple tapeouts for multiple projects (350nm) simultaneously. S enior Physical Design Engineer (Senior Layout Designer), Marvell Semiconductors, Inc. September 13, 1999 - December, 1999
Custom Layout Design, from floorplanning to tapeout, including stdcell layout, using Cadence layout tool. Auto P&R, from floorplanning to tapeout (including LVS/DRC fixes), block-level / chip-level, using Astro. Accomplishments
● Fully custom design stdcell cell layout library set.
● Auto P&R, from floorplanning to tapeout (including LVS/DRC debugging / fixes), block-level / chip-level, using Astro.
● Multi-tasking - doing multiple tapeouts for multiple projects (350nm/250nm) simultaneously.
● Training junior layout designers.
CAD Designer (Physical Design Engineer), Marvell Semiconductors, Inc. 1259 Faiweather Lake CMN
San Jose, CA 95131
E: ***********@*****.***
Jason Hu
Senior Physical Design Engineer
December 1999 - January 2001
Auto P&R, from floorplanning to tapeout (including LVS/DRC fixes), block-level / chip-level, using Astro. Accomplishments
● Fully custom design stdcell cell layout library set.
● Auto P&R, from floorplanning to tapeout (including LVS/DRC debugging / fixes), block-level / chip-level, using Astro.
● Multi-tasking - doing multiple tapeouts for different projects (250nm/180nm) simultaneously.
● Training junior layout designers.
Senior CAD Designer (Senior Physical Design Engineer), Marvell Semiconductors, Inc. January 2001 - January 2009
Auto P&R from floorplanning to tapeout (including LVS/DRC fixes, timing-driven P&R), block-level / chip-level, using Astro/ICC.
Accomplishments
● Auto P&R, from floorplanning to tapeout (including LVS/DRC debugging / fixes), block-level / chip-level, using Astro.
● Multi-tasking - doing multiple tapeouts for different projects (90nm/65nm/35nm) simultaneously.
● Start timing driven P&R.
● Training junior auto P&R designers.
Staff CAD Designer (Staff Physical Design Engineer), Marvell Semiconductors, Inc. January 2009 - July 2015
Auto P&R from floorplanning to tapeout (including LVS/DRC fixes, timing-driven P&R), block-level / chip-level, using Astro/ICC.
Accomplishments
● Auto P&R, from floorplanning to tapeout (including LVS/DRC debugging / fixes), block-level / chip-level, using Astro.
● Multi-tasking - doing multiple tapeouts for different projects (28nm/14nm) simultaneously.
● Start Power Analysis
● Training senior auto P&R designers.
EDUCATION
Sacramento High School, Sacramento, CA, 1985 - 1989 S acramento City College, Sacramento, CA 1989 - 1995 1259 Faiweather Lake CMN
San Jose, CA 95131
E: ***********@*****.***
Jason Hu
Senior Physical Design Engineer
SKILLS
● Able to use Cadence Layout tool.
● Able to use Synopsys Astro/ICC auto P&R tool.
● Able to handle from block-level to chip-level design and able to handle multi-tasking.
● Working with front-end designers very closely and smoothly.
● Very strong on the backend and able to debug LVS/DRC and do the relevant fixes;
● Little weak on CTS.
REFERENCES
Available upon request.
1259 Faiweather Lake CMN
San Jose, CA 95131
E: ***********@*****.***
Contact this candidate