cmos,digital design,layout,verilog,system verilog,oops,shell and perl

V. VISHNU PRIYA

E-mail: *******************@*****.***

Mob: +91-903*******

CAREER OBJECTIVE

Seeking a career as ASIC VERIFICATION ENGINEER within an organization, where I can contribute my skills for organization’s success and synchronize myself with new technology while being resourceful, innovative and flexible.

TECHNICAL COURSE

Completed The Post Graduate Diploma in VLSI Design & Technology using Cadence EDA Tools at Industrial Training and Research Institute (ITRI), Bangalore.

CORE COMPETENCIES

Hardware Languages

Verilog & System Verilog.

Verification Methodology

UVM

Scripting Languages

Shell (TCSH),PERL & PYTHON.

Operating Systems

Windows & Linux (REDHAT).

Others

Command Line Interface (CLI), Knowledge in CMOS and Digital Design, understanding of full custom design flow and physical design flow.

EDA TOOL EXPERIENCE

CADENCE (NCVERILOG, SIMVISION, RTL COMPILER, SOC ENCOUNTER, VIRTUOSO & ASSURA)

PROJECTS ITRI

1)PROJECT TITLE: SYSTEM VERILOG VERIFICATION ENVIRONMENT FOR A MEMORY BLOCK.

Learning Objective: To get familiar with verification environment using system verilog.

Description: In this project we have done RTL coding for the memory block in the first stage. In the second stage we have created verification environment for the RTL code to test all possible scenarios using system verilog. Several blocks such as Base, Transactor, Driver, I/O monitor and checker with the help of OOPS concepts were created for verification environment.

2)PROJECT TITLE: RTL CODING FOR AMBA – APB PROTOCOL.

Learning Objective: To get familiar with RTL coding.

Description: In this project we have done RTL coding for APB protocol in the first stage. We have analyzed how the communication will happen between master and slave peripheral devices.

3)PROJECT TITLE: RTL CODING AND FSM DESIGN FOR 8 – BIT SEQUENTIAL MULTIPLIER USING VERILOG.

Learning Objective: To get familiar with RTL coding and FSM design.

Description: In this project we have done RTL coding for 8 – bit sequential multiplier for the given specifications. The behavior of multiplier is analyzed with FSM design.

4)PROJECT TITLE: TEXT PROCESSING AND TEXT MANIPULATION OF PACKAGE AND TEST FILES USING PERL SCRIPTING.

Learning Objective: To understand the syntax of PERL and perform various text processing and text manipulation operations on given package and test files.

Description: Study was done on syntax of PERL with respect to data context, operators and variables. How to use conditional statements, looping, substitution, file operation, regular expression and subroutines was analyzed through examples. Through the above study we have performed text manipulation and text processing.

Platform: REDHAT Linux

PERL version: V 5.8.8

PROJECTS ACADEMICS

1)PROJECT TITLE: BRAIN TUMOUR CLASSIFICATION USING DISCRETE CURVELET TRANSFORM AND PROBABILISTIC NEURAL NETWORK.

Description: The Computer Aided Diagnosis (CAD) system employs automatic tumour classification based on texture feature extraction and characterization into malignant and benign tumours. The MRI brain image will be classified automatically by Probabilistic Neural Network and texture features. For Pattern analysis and recognition, Fast Discrete Curvelet Transform based on co-occurrence features are used here.

EDUCATIONAL QUALIFICATION

Degree/ Exam

Subject

Institution

University/Board

Year

Score

Diploma

VLSI Design

Industrial Training And Research Institute(ITRI), Bangalore

ITRI

2016

B. Tech.

ECE

Narayana Engineering College

JNTUA

2015

80.23%

Intermediate

MPC

Narayana Junior College

Board Of Intermediate

2011

90%

CBSE

-

Little Angels Public School

CBSE

2009

80%

PERSONAL DETAILS

Date of Birth

04/04/1993

Gender

Female

Indian Languages known

English,Telugu & Hindi

Hobbies & Interests

Dancing, Listening to music and Gardening

DECLARATION

I hereby declare that the above mentioned details are true to the best of my knowledge.

PLACE: Bangalore V. VISHNU PRIYA

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