Physical Design engineer, Floorplanning, Place and Route, STA, DRC

JUHI NARKHEDE

**** ***** *** **, ****, NC- ***** 919-***-**** **************@*****.*** LinkedIn Currently working as a Physical Design Engineer-intern at Cadence Design Systems. Looking for full-time opportunity to work as Hardware engineer. EDUCATION:

Masters of Science in Electrical Engineering GPA: 3.6 /4 North Carolina State University May 2016

Bachelor of Engineering in Electrical Engineering GPA: 3.7/4 Fr. C. Rodrigues Institute of Technology, University of Mumbai, India May 2014 COURSES

ASIC Verification(ECE 745)

ASIC Design(ECE 520)

Power Electronics(ECE 534)

Computer Design Technology (ECE 521)

Analog Electronics (ECE 511)

Analog to Digital Converters(ECE 792)

Power Management Integrated Circuits(ECE 734)

Product Innovation Lab (ECE 592)

SKILLS

Languages: System Verilog, Verilog, Tcl, Verilog A, C++, C, Python and shell scripting. Skills and Tools: Floorplanning, Static Timing analysis, Clock Tree Synthesis, Physical Verification, Functional Verification, Coverage planning, System Verilog Assertions, RTL Tools: Cadence Innovus, Tempus, PVS, Virtuoso, Synopsys DC, QuestaSim, MATLAB, AutoCAD. Attributes: Ability to work as an individual as well as in a team, quick learner, and detail oriented and hardworking. WORK EXPERIENCE

Cadence Design Systems, Inc. September 2016 – present Physical Design Engineer - intern

Contributed to the successful tape-out of 28nm technology node

Designed optimal floor plans.

Took blocks through placement, clock tree synthesis and routing.

Closed timing for blocks (setup and hold).

Implemented physical verification of blocks (LVS, DRC and ANTENNA).

Developed and maintained Tcl scripts for common tasks to improve work efficiency ACADEMIC PROJECTS

Functional Verification Of L2- C3 Microcontroller: (System Verilog, QuestaSim)

Designed a layered Testbench using System Verilog for verification of Pipelined LC3 Microcontroller. The test bench consist of class generator, driver and golden reference models of LC3 microcontroller.

Successful use of Constrained Random Testing and Directed Test Cases to achieve 100 % functional coverage and cover all corner cases. Used Mailboxes to transfer data between test bench classes. Jacobi Iteration for Sparse Matrix Solver: (Verilog, ModelSim, Design Vision)

Designed an ASIC hardware unit of the Jacobi Iteration method for a Sparse Matrix solver to solve a system equation YV = I. The

‘Y’ is a 1000 x 1000 matrix and ‘I’ is a 1000 x 1 vector.

Performed Synthesis to meet setup and hold constraints. The clock speed was 24ns and the total area was 19790.66 m2. Used Pipelined design to maximize the clock frequency.

Cache Hierarchy Design: (C++, Linux)

Designed a generic cache module that can be used at any level in memory hierarchy. Simulated L1 and L2 cache for replacement policies such as LRU, FIFO and LFU and for non-inclusive, inclusive and exclusive policies.

Observed the effect of different replacement and inclusive policies and various cache sizes on cache performance. Dynamic Instruction Scheduling: (C++, Linux)

Developed a simulator for out-of-order execution fetching and dispatching N instruction per cycle.

Analyzed processor parameters by varying the Reorder buffer size and the issue queue size.

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