Contact Number: 469-***-**** NAVKIRAN KAUR PANDHER

Email : acysij@r.postjobfree.com https://www.linkedin.com/in/navkiranpandher

EDUCATION:

The University of Texas at Dallas, Richardson, Texas Graduation: December 2016

Masters of Science, Electrical Engineering (Concentration: Circuits and Systems)

Coursework: VLSI Design, Computer Architecture, ASIC Design, Advanced Digital Logic, Design Automation, Testing and Testable Devices, Analog Integrated Circuits.

Punjab Technical University, Jalandhar, India Graduation: July 2013

Bachelor of Technology in Electronics and Communications Engineering

TECHNICAL SKILLS:

Tools: Xilinx ISE, Modelsim, Simplescalar, Matlab.

Cadence: Virtuoso, Encounter, LVS/DRC.

Synopsys: Primetime, Tetramax, IC Complier, Design Vision, HSPICE

Languages: Verilog, VHDL, Assembly language, C, C ++, Perl, Tcl.

WORK EXPERIENCE:

Hardware Test Intern at SVTRONICS Inc. (June 2015 -August 2015, January 2016 – May 2016)

Testing the functionality of AFE7500 RF communication Boards by Texas Instruments using GUI, spectrum analyzer and signal generator

Troubleshooting Receiver and Transmitter of AFE7500 to improve the functionality of erroneous Boards.

Evaluating and Recommending components for fixing the functionality of these Boards.

Assisted in Layout Support Section.

ACADEMIC PROJECTS:

Design of Mini Stereo Digital Audio Processor (MSDAP)

Designed an ASIC chip implementing FIR filter achieving necessary Chip parameters. Implemented the RTL model using Verilog coding.

Achieved all the desired design specifications such as 2.3mW Power with 77% core utilization.

Used IC compiler for Final Physical Design, Timing and Power Budget Analysis of Chip.

Simulated Annealing Algorithm for circuit partitioning and standard cell placement using C language

Implement Simulated Annealing Algorithm for circuit bi-partitioning to achieve 84% reduction in initial cut-size. Used same algorithm for standard cell placement and achieved about 75% reduction in initial wire length. GCC complier was used to compiling the C code.

Design and Implementation of a 16-bit ALU using IBM 130nm Technology

Designed a 16 bit ALU using RTL code and synthesized using Design Vision. Created standard cells using CADENCE virtuoso followed by DRC/LVS.

Performed floor plan, placement and routing using Encounter. STA (Static Timing Analysis) was performed using Primetime.

Cache Memory Design for Alpha Microprocessor

Designed a Cache with optimum configuration based on cost function and the CPI value for benchmarks – CC1, Anagram and GO using Simple Scalar tool. Perl Script was written to extract cost and CPI value.

Performed optimization for Block size, Associativity and Replacement policy for different benchmarks.

Improve Fault Coverage for Sequential Circuits using SCAN DFT

For ISCAS89 s27 benchmark, replaced normal flip-flops with scan flip-flops using Scan DFT Methodology.

Used Tetramax to read generated netlist, generate Fault patterns and obtained 100% Fault Coverage.

Fault Simulation and Pattern generation

Implemented and Synthesized Verilog code for a given digital circuit using Design Vision.

Used Tetramax and Performed ATPG to determine Test vectors, Stuck at faults and Fault coverage.

Designed two stage Opamp

Designed 0.35um CMOS technology differential input and single ended output Opamp and used cadence design tools such as Analog Design Environment(ADE), Spectre & Virtuoso Schematic Editor to optimize and measure various parameters.

Achieved required specifications such as Gain of 85 dB, consuming just 0.3mW of Power, 61 degrees of Phase margin and Average Slew Rate of 15 V/us.

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