Engineering Design

CHAFIKA MOUSSAOUI

**** ********** ******,

Apt **3, Philadelphia, PA 19118

Phone: 267-***-****

*******.*********@*****.***

OBJECTIVE

As a bilingual (English-French) Electronics Engineer specialized in chip design, with a research and innovation background, I aim to utilize my skills to overcome a high technology sector challenges.

TECHNICAL SKILLS & COMPETENCIES

Programming: EDA tools, Java, C++, VHDL, Pspice, CAD tools, Matlab & Simulink, Linux

Communication: Data Transfer, Storage and Protocols (TCP/IP & ISDN)

Database: Microsoft Access and Oracle

Signal Analysis: Digital and Analog Signal processing.

Instruments: Oscilloscope & Digital Meter, Logic & Spectrum Analyzer, Function Generator and Power Supply

Engineering background: Earned an extensive number of credits in Mechanics, Mathematics (differential and Integral Calculus), Chemistry, Physics, Electronics and Electricity

Comprehensive knowledge of electronic engineering principles and concepts as well as established analytical tools

Well versed in analog and digital design

Strong knowledge of mathematical concepts and fundamentals of geometry

Excellent analytical, troubleshooting and time management skills

Ability to communicate effectively with strong organizational and problem solving skills

P R O F E S S I O N A L E X P E R I E N C E

2000-2014

System-on-Chip Design Center (SCDC)

Temple University Philadelphia, PA.

Devised a Monte Carlo technique with Matlab Simulink to estimate power dissipation and localize hot spots on ICs. As a result of this technique an innovative way to improve power management in VLSI chips was established and researched.

Drafted PCBs layouts with Pspice and Tanner EDA tools for simulation and design

Led and monitored a team of engineering students in the lab and assessed their results using oscilloscopes, digital multimeters and logic analyzers

Used a variety of probabilistic & statistical techniques in different research projects

Projects

1.Power Dissipation in VLSI

Estimated Static and Dynamic Power Estimation for SoC chips using industrial tools.

Used Spice simulation to simulate circuits of over 20K cells and thousands of memory elements.

Simulated with a Monte Carlo technique to determine power density and localize the hot spots.

Calculated Power Dissipation for high-density CMOS gate arrays and CMOS Asics.

Analyzed the thermal behavior and reliability of key electronic components on PCB boards

2.Cross Talk and Signal Integrity Analysis

Analyzed crosstalk of coupled transmission lines

Analyzed noise coupling for a high speed multilayer printed circuit board

Analyzed timing and signal integrity in a cell based SOI design

3.PCB Layouts

Analyzed PCB layout VIAs effect on power supply performance

Analyzed the integrity of PCB signals

Researched 3D PCB converter technology

4.Digital signal processing

Analyzed various speech signals

Studied the design and development of parallel DSP processor architectures

Designed the architecture of IIR and FIR filters and an hybrid IIR-FIR echo canceller for wireline applications

Faculty

Temple University - Penn State University - Chestnut Hill College

Lectured in College Algebra, Calculus and Statistics

Managed and Advised students and designed curriculum

Motivated students to engage in active learning

Implemented lesson plans involving HTML, XHTML, web technologies, and graphic design and coached students in the design process.

Achieved the final project design of Academic and Business Web Sites with the students that were successfully launched and effective.

Lectured in Java and C++ and conducted labs in Database Design and Management

Assessed students progress daily

Managed a database Client/Server system using PL/SQL and Oracle 9i

E D U C A T I O N

M.S., Electrical and Computer Engineering

Temple University PA, 2002

B.S., and M.S., Control Systems Engineering

Science and Technology University, 1997

ACHIEVEMENTS AND PUBLICATIONS

C. Moussaoui, Z. Delalic, J. Chen, D. Silage, “Numerical and Experimental Simulation of Electro-Thermal Behavior of VLSI Chips”. IMAPS proceedings, October 2001, pp. 218-223

C. Moussaoui and L. Bai, “A Monte Carlo Approach for the Estimation of Power Dissipation in VLSI chips”. IMCS proceedings, June 2002, pp.49-53 and Best Paper Award-IMAPS Symposium, Oct. 2002

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