Engineer Testing

Jignesh Modi

*************@*****.*** 814-***-****

**** ******* *****, ******* *******, IL 60169

OBJECTIVE

To obtain a full-time position for utilizing my background in the field of Electrical Engineering, Embedded Software Engineering and Testing Engineer involving research and development. SUMMARY

One year experience in the Software testing and Application testing.

More than two years of experience in PCB designing with cadence tool, System analysis, design and Quality Testing.

More than one year of experience in lab monitoring and maintenance.

Experienced in Automated Technical Manuals and UAT.

Experienced to prepare the codes in C and C++ for embedded systems on PIC 32 environments.

Experienced in MATLAB R2014a, Cadence Allegro PCB designing, Cogenda T-CAD 1.8.2, National Instrument’s’ Lab View.

Experienced in Software Testing (Manual and Automation Testing) in high paced software development environment using Agile & Waterfall development methodologies.

Experienced in the different types of testing that include SDLC, STLC, Firmware Testing, System testing, Integration testing, Functional testing, Smoke Testing, Black Box Testing, Manual and Regression testing with automated testing tools.

Experience in Writing Test plans, Use Cases, Test cases, and System design & Requirement analysis..

Keen interest in Designing, Analytics, Reporting and Test Engineer. WORK EXPERIENCE

Lab Assistant, Gannon University, Pennsylvania August-15 to December-16

Responsible for monitoring the lab equipment (DSO, Digital Power Supply etc.) and its performance.

Maintain all the computers in the lab and perform the troubleshooting for the inter- networking.

Prepared PCB design for some special projects in the school.

Test the lab equipment (DSO, Power Supply etc.) and prepare the test documents.

Supported various LAN environments consisting of cisco 6500 switches Technical Assistant, Real-tech Automation, Gujarat, India August-14 to May-15

Responsible for Testing the components and final product.

Responsible for the PCB designing for the Front panel of the PLC.

Responsible to verify the final product match all the requirements.

Perform the system testing, Integration Testing, Manual and Regression Testing,

Responsible for preparing Test Plans, Use Cases, Test Cases and maintain the requirements.

Prepare the manual and other supporting documents for the product.

Supervise a supporting staff.

Intern, Volansys Technologies, Gujarat, India August- 13 to April- 14

Testing the Software and report to the supervisor.

Prepare the manual and other supporting documents for the report.

Performing Manual Testing and prepare the test reports.

Perform the Agile Testing for software testing.

Prepare the documents for test procedures, test specs and test reports. EDUCATION

MS Computer Software Engineering December 2016

Minor: Wireless Communication / Software Testing GPA: 3.91 Gannon University, Erie PA

M. Tech. Electronics and Communication August 2014 Minor: Communication Mathematics GPA: 3.84

Ganpat University, Kherva, Gujarat, India

BE Electronics and Communication June 2012

Minor: Calculus, Advance Mathematics GPA: 3.47

Gujarat Technological University, Ahmedabad, Gujarat, India ACADEMIC PROJECTS

Title: Design Task Management Technique based on Shared Resources. Aug-16 to Dec-16 Organization: Gannon University, Erie, PA

Description: Task Management for optimum usage of the shared resources. The algorithm prepared for the task management is developed on PIC 32 controller board. The algorithm assigned a task to the scheduler to fulfill the requirements.

Title: Design EMS and ECU section for Engine Control April-16 to Aug- 2016 Organization: Gannon University, Erie, PA

Description: To design the EMS and ECU section for engine control and develop the embedded system codes on PIC 32 controller board. The EMS and ECU section is verified by using the DSO. The codes of EMS and ECU section are simulating on MPLab IDE simulator. Title: Design of Si-Ge TFET to improve Sub-Threshold Swing (SS) and increase the drive current

(ION). June -13 to Aug 2014

Organization: Ganpat University, Kherva, Gujarat, India Description: Design the 40 nm Si-Ge TFET in Cogenda T-CAD and obtain the value for Sub- Threshold Swing and Drive current and compare it with previous results. By modifying the design, I found the more nearer value to the ideal TFET.

Title: Design Arduino based the Smart Farm. June-11 to May 2012 Organization: Gujarat Technological University, Ahmedabad, Gujarat, India Description: Prepare the Arduino codes for the semi-autonomous farm that reduce the human efforts and improve the utilization of the available resources to get maximum output. The whole system governs by Arduino processor and it control all the sensors, servo motors, water pump etc. COMPUTER SKILL

Simulator: Cogenda T-CAD 1.8.2, MATLAB R2014a, MPLab IDE v8.76, GNS3, National Instrument’s’ Lab View, Cadence Allegro PCB designing Operating System: Windows XP\7\Vista\10

Languages: VHDL, C, C++, Embedded C, Python, HTML

Testing Tool: HP Testing Suite (Quality Center. Quick Test Professional) Applications: Microsoft office suite

RELEVANT COURSES

Embedded System Design Control Systems

Circuits and Networks Networking Essentials

Embedded Kernel Digital Communication

Digital Signal Processing Data Communication & Networking Object Oriented Programming Systems FPGA

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