Engineer Design

Dipayan Mazumdar

** ********** *****, ******* *** 1X8

E mail : ******************@***.***

Contact : 437-***-****

SUMMARY

New employee in the CNC machining industry studying at IMTT, Missisauga. I have mastered skills like Solidworks, MasterCAM and G-code programming for CNC machines, Fanuc and Siemens. Education

PhD in EE, 2016, Coventry University, UK

MS in EE, 1988-1990, University of Alabama, Tuscaloosa, AL, USA

BE in EE, 1986, Jadavpur University, Calcutta, India PATENTS: 2011 to Date

“Data interface circuit”, US Patent Granted, Number 8451147, Issue date 28th May 2013

“A Taylor Series based Direct Digital Synthesizer”, US patent Granted, Number 8570203, Issue date : Oct 29th,2013

“A Taylor Series based Direct Digital Synthesizer”, US patent Granted, Number 9,100,044, Issue date : April 4th 2015

“Wavelet processor” US Patent Granted, Number 9197902 Issue date : November 24th 2015

Japanese Patent Granted number No. 5640157 on “Multicore processors for Wavelet processing”, Issue date December 10, 2014

Korean Patent no. 10-149****-**** Title : “Data Interface Circuit” Issue Date : 05/02/2015

Korean Patent no. 10-145****-**** Title : “Wavelet processor” Issue Date : 15/10/2014

Chinese Patent No. CN103026349 (B) Title “ Data Interface Circuit ”, Issue Date : April 4th, 2016

2013 - 234/CHE/2013 “Efficient Direct Digital Synthesizer”, India, Filing date Jan 7th 2013

2010–2473/CHE/2010 “Matrix Inversion method and apparatus”, Filing date: August 26,2010

2010-3635/CHE/2010: “A systolic array based Wavelet processor”, Indian Patent Office Filing date : July 16,2010

2015 : “Image Rejection Mixer with reduced Amplitude and Phase Mismatch”, Co-inventors Varun D., Govind R. Kadambi, Indian Patent Office

German Patent Application No. DE 112********* T5 pending filed in 2013 Tile : “Datens chnittstellung”

EXPERIENCE

Institute of Machine Tool and Technology, Toronto May 2016 – till date ongoing

Trained CNC programming course. At the premier institute in Canada. Able to manually program G code Fanuc 3-axis machines- b oth Milling and Lathe. Strong in Solidworks and MasterCam toolpath programming. Designed toolpaths using Mastercam .

Current : other New company in Impact aborbing materials. Associate Professor Koneru Lakshmaiah University May 2015 – May 2016 2

Teaching VLSI design courses

Consulting Senior Scientist Ienergy Ltd. June2013 – May 2015

Design of Phasor Measurement units (PMU) for Power systems – 1 new Patent on PMU

Controllers for Voltage-VAR-Wattage controllers in Power Distribution Melange Systems, Bangalore, India June 2011-May2013 Job Title: Head of Patents and Inventions.

Completed and delivered a group of 8 RF board level systems for 802.11 WLAN, Zigbee, ISM band

(865 MHz), 2.45GHz and 5.8 GHz. Includes a WLAN module, 2.45GHz TX/RX board, 5.8 GHZ TX/RS board, GPS board and RF switching board (2.45/5.8GHz). Managed a team of 5 engineers on the project.

PCB design for RF circuits using FR-4 and Rogers material up to 5.8 GHz frequency

Contributory Areas – IEEE 802.11a/b/g wireless LAN

Design of RF TX-Rx path for 5.8GHz and 2.45 GHz for WLAN board for 27dB( 1 Watt peak output power)

WLAN networking software integration 802.11a/b/g for CDOT

Navik GPS board for CDOT- designed PCB board

Motorola Zigbee board for CDOT

RF board design and analysis for 5.8GHz- IEEE802.11a – deisgn and testing.

FPGA programming using Verilog and Xilinx SysgenTM tools for Direct Digital Synthesis M.S. Ramaiah School of Advanced Studies Sept 2008-June 2011 Assistant Professor

Ran multiple Senior level Corporate Trainings on DSP, Digital Communication and VLSI design Teaching – FPGAs, DSP, Digital Communication, Computer Architecture and Parallel Processing, Directed 4 Masters thesis in RF engineering using ADS®, Genesys and Agilent System View®-2008-2011

Highly proficient in the modeling of end to end receiver designs using AWR Microwave office, Agilent Systemview® and Matlab Communication and Control Toolbox®.

Design of a Phase and Amplitude mismatch correction scheme based on a second order Haven’s technique – DRDO project ISCAS paper, 2011

Design of a down-conversion circuit for 2.45GHz using a Gilbert gain cell mixer

Design of amplifier Linearization with and without digital pre distortion for Saleh, Ghorbani and Raab models, 2009.

Cadence Design Systems April 2006 – June 2008

Senior Product Engineer

Manage projects for customers

DFT – scan insertion, XOR compression insertion, OPMISR compression insertion, Memory Built in self Test, Cadence ATPG tools, ATPG flow development

Deliver ARM CORE reference designs

Sasken Ltd. June 2005-April 2006

3

VLSI Team Lead

Project - Bluetooth + SDIO + FM Radio Wireless Design. Complexity 2.5M gates.

Synthesis – Synopsys Design Compiler, Prime-Time STA, Formal Verification.

Formal Verification – using Synopsys Formality. Formality scripts development

Physical synthesis of for a wireless chip using Synopsys Physical Compiler Major contribution – Developed a fully configurable Formal verification environment Synopsys Inc., Bangalore June 2003- June 2005

Senior Application Consultant

Front end of DFT/ATPG and Formal Verification tools

Synopsys DFT compiler, Synopsys ATPG(Tetramax) for multimillion gate chips.

Performed ATPG and verification using Tetramax and VCS for 3 million gate Wireless ASIC.

Synopsys Design Compiler, JTAG and PrimeTime – STA Intrinsix Inc., Ottawa, Canada August 2000- June 2003 Senior VLSI Design Engineer

Logic Synthesis using Synopsys DC and Physical Synthesis of MPEG coder-decoder design with 3M+ gates

Scan insertion, ATPG,Memory BIST, and ATPG of a 4 million gate networking ASIC Significant Contribution- Developed a method to generate PDEF for physical synthesis Chartered Semiconductor, Singapore May 1994 – June 2000 Principal Product engineer

Team lead for test chip validation, test program development and analysis of test chips - Memory and logic for 0.35um/0.25um/0.18um processes

Siemens Ltd. Singapore 1994-1997

VLSI design Engineer

Project : Specification and Design of a Speakerphone CODEC Chip 250K, V.34 Modem chip Arcus Ltd. Bangalore, India 1991-1993

VLSI design Engineer,Project : Specification and Design of 1024X1024 Time Switch and Space Switch REFERENCES

Dr. Govind R. Kadambi, Pro Vice Chancellor, M.S. Ramaiah University of Applied Sciences Rawle Boodoo Esq., Institute Director, IMTT Canada CELL: 437-***-**** • E mail : ******************@***.*** NO . 9 3 SEDGEMOUNT DR IVE, TORONTO, M1H 1X8

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