Design Engineering

Naveen Prabu Palanisamy

**** **** ****** *** ***, Sacramento, CA- 95825 PH: 916-***-**** Email : acymt3@r.postjobfree.com OBJECTIVE:

To obtain an entry level position in Digital Design/Verification/Validation and Computer Architecture where I can learn, work and groom myself and help the organization to achieve goals. EDUCATION:

Master of Science in Electrical Engineering, CSU Sacramento, December 2016. GPA – 3.8/4 Bachelor of Engineering in Electronics and Communication Engineering, Anna University, India. GPA – 3.6/4 Courses: Hierarchical Digital Design Methodology Advanced Computer Architecture Advanced Timing Analysis and ASIC Design Advanced Logic Design Digital Integrated Circuit design Microprocessor and its application Micro-Computer System Design VLSI Design

Numerical Analysis Embedded Systems

KNOWLEDGE AND SKILLS:

Hardware Languages : Verilog, System Verilog.

Programming Languages : Java, C, C++, Matlab, SQL. Scripting Languages : Perl, Python.

Software Tools : Synopsys VCS, DC, Primetime, Cadence Virtuoso, Multisim, Xilinx ISE, Eclipse IDE. Protocols : Cache Coherency protocols, PCI, USB, SATA, SAS, RAID technologies. PROJECT EXPERIENCE:

Master’s thesis: - Filtering of Inertial Measurement Unit (IMU) data using Kalman Filter:

Modeling a Kalman Filter in MATLAB which predicts the position, velocity, distance and error covariance from the measured accelerometer data’s in X, Y and Z axis from IMU and estimates an exact position of object in accordance with Kalman gain. Analyzing the applications of Kalman filter for existing IMU data from a moving object in 2D and 3D. Design and Validation of Pipelined Floating Point Multiplier in System Verilog:

Designed, modeled and validated a Pipelined Floating Point Multiplier unit that computes the product of two 32-bit single precision floating point numbers represented in IEEE 754 format. Simulation and verification was performed in SYNOPSYS VCS TOOL. RTL is synthesized in SYNOPSYS DESIGN COMPILER (DC) TOOL. A layered test bench with an environment setup is created to validate and verify the design and also functional coverage is done. Design of an Asynchronous FIFO Buffer in Verilog:

Designed and modeled an Asynchronous FIFO circular buffer which had a capacity of holding 128 32-bit words. Synthesized the design in SYNOPSYS DESIGN COMPILER (DC) TOOL to obtain the optimized gate level net-list. The design is optimized for timing and area to get zero timing slack. Then code coverage is also done. Microprocessor Static Timing Analysis using Synopsys Primetime:

A new QTM model is created in SYNOPSYS PRIMETIME TOOL, then optimized and generated area and timing reports, performed checks for setup and hold time slack. Analysis of an unmapped design by writing TCL scripts for different constraints like operating conditions, Wire load Model, Clock uncertainty and latency are performed. Design and Verification of 4 x 3 Memory, 4-bit Counter and a 32-bit ALU in Verilog:

Designed an ALU which can handle two 32-bit inputs and a 4 x 3 RAM. Created an automatic input test vectors to Verilog Test bench using Perl Scripting. Perl Script emulated the 4 x 3 RAM design and ALU to produce output results and compared with the DUT results. Verification performed with full code coverage in SYNOPSYS VCS. Design, Simulation and Layout of Bubble Suppress and Decode logic of 0.18μm CMOS:

Design was done for a 4 bit ADC using the CADENCE VIRTUOSO. Logic gates like NAND, NOR and NOT gates and D-flip- flops were designed as part of cell library and used in the design. Design was verified to DRC and LVS. Interfacing SPARTAN 3E FPGA with LCD using Xilinx ISE:

Code was written in Verilog HDL for performing arithmetic calculations and displaying names on LCD screen of Spartan 3E FPGA. Worked on Xilinx ISE to program the Verilog code and to simulate the design. PROFESSIONAL EXPERIENCE:

Project Trainee Salzer Electronics, India [JUL’13 - APR’14]

Developed a system of automating the temperature test of contactors. A module using PIC16F877 is programmed in Embedded C and interfaced with Desktop and temperature graphs are monitored and values are stored in a database. PAPER PRESENTATION & ACTIVITES:

Presented a paper on “Design of Second level caches using SRAM and EDRAM” at CSUS 2016.

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