SATISHKUMAR RAJENDRA GOUDNOOR

*** * ******** ***, *********, CA 94085 +1-626-***-**** acyj3f@r.postjobfree.com

PROFILE SUMMARY

Around 4 years of professional experience in Pre-Silicon Validation/Verification of various SoC’ and IPs.

Proficient in C/C++ programming and Assembly Language programming.

Expertise in Verilog and System Verilog Coding for development of and asic verification environment.

Experience in verification of ARM based SoC. (System on Chip) at RTL level and gate level.

Have Expertise knowledge of FPGAs and ASICs.

Good working knowledge of Python coding.

Good working knowledge of communication protocols like I2C, SPI, RS232, USB, UART and CAN.

Very good exposure to shell scripting and python scripting.

Knowledge and experience of Linux User Space programming, multithreaded programming, Linux Memory management.

Experienced in ARM7 and ARM9 architecture.

Good working knowledge of DDR and PHY Blocks.

Experience in creating environment for GLS.

Good expertise in developing and implementing testcases to verify the modules.

Ability to learn and master new technologies with good analytical and problem solving skills.

TECHNICAL KNOWLEDGE AND SKILL SET

Operating Systems : UNIX, Linux, Windows CE

Languages : Verilog, VHDL, System Verilog, C++, Assembly language, Perl scripting,

python, Linux Shell Scripting

IDE : Eclipse, Visual Studio, Kiel, IAR, Xilinx

Protocols : SPI, I2C, AXI, CAN, USB, UART, PCI, RS232, TCP/IP

Tools : Xilinx, NC-Verilog, Simvision, and Synopsys VCs, Modelsim

TRAININGS ATTENDED

Digital Design and Synthesizable HDL

Verification Essentials

HDL Based Verification

Real Life Lab – Design and Verification

Perl

PROJECT EXPERIENCE

1#Project: “Development of application for integration Sxm module in Head unit of Mercedes cars”

Mercedes Benz research and Development North America, Sunnyvale, CA

July 2016-Jan2017

Responsibilities:

Was part of team, which was involved in implementation of sxm module in Head unit of next generation cars.

I was responsible for development of application in C++ in the head unit.

Gauging the performance of the CPU by doing profiling.

Analyzing the features and functions in radio module.

Development and reuse of IF1 and IF2 protocols.

2# Project: “Modified MIPS lite (MML) Multi-cycle Design Project, CSULA”

May 2015 – Aug 2015

Responsibilities:

An academic project in which a group of 4 were involved in designing a MIPS architecture ISA using Verilog language.

I was primarily responsible for coding part.

Successfully implemented a 16 bit multi cycle data path using Verilog language.

Completed the entire coding in less than 48 hours without errors.

2# Project: “Verification of Multicore SoC.”

Texas Instruments, Bangalore India

Project Engineer

May 2013 – Aug 2014

Responsibilities:

Worked on IPs of a 28nm SoC. for Texas Instruments Client.

Filed bug reports, verified RTLfixes, analyzed test results and performed coverage analysis.

Wrote and executed verification test plans (block and chip level) for multiple sub-blocks within ASICs

Development of Verification plan and Test plans.

Functional and coverage coding.

Debugged RTL using simulators like NC-Verilog, Simvision, and Synopsys VCS.

Involved in writing and modifying Perl scripts.

Executed Gate level simulation for my modules.

Was part of team to create environment for GLS

Developed Python scripts to automate regression process.

Independently developed and maintained the automated system level test environment in UNIX (using PERL and Shell scripts).

Designing System Verilog OVM Test Bench and infrastructure for verification of DDR PHY.

Worked on first base/template test for the PHY which is used as reference to build other tests.

Responsibilities included: execute top-level regression test cases in automated mode, investigate and debug defects, elevate issues to designers and maintain the verification database.

3# Project: “Verification of Multicore SoC.”

Texas Instruments, Bangalore India

Project Engineer

Feb 2012 - Apr 2013

Responsibilities:

Worked on IPs of a 28nm SoC. for Texas Instruments Client.

Executed top-level regression test cases, investigate and debug defects, elevate issues to designers.

Filed bug reports, verified RTLfixes, analyzed test results and performed coverage analysis.

Completely handled the DDR module along with PHY module.

Worked on IPs which enhanced the Main processor (DSP) performance.

Analyzed python scripts.

Verified the functionality of the Encoder DMA.

Developed a testplan and setup the testbench and the environment.

Functional and Code coverage coding.

Debugged RTL using simulators like NC-Verilog, Simvision, and Synopsys VCS.

Involved in writing and modifying Perl scripts.

Responsibilities included: execute top-level regression test cases in automated mode, investigate and debug defects, elevate issues to designers and maintain the verification database.

4# Project: “Ethernet Controller Design and Verification.”

Texas Instruments, Bangalore India

Project Engineer

Sep 2011 - Oct 2011

The MDIO interface is a two-wire, serial interface, clock and data. MDIO is used to connect a management entity and a managed PHY for the purposes of controlling the PHY and gathering status from the PHY.

Responsible for design logic block for the MDIO slave, developed the RTL code and verify the same using Verilog.

5# Project: “H.264 baseline video encoding using TMS320C6713 DSP.”

RNSIT Bangalore

Feb 2011 - Jun 2011

This was an academic project in which our team converted a YUV video input file into a highly compressed H.264 output while retaining the quality of the output using a digital signal processor, Leading our team to win the best Project award in the college.

EDUCATION

California State University, Los Angeles, California .GPA: 3.91/4 Sep, 2014 - Mar, 2016

Master of Science in Electrical and Computer Engineering

Emphasis on Communication and Networks

Visvesvaraya Technological University, India. GPA: 3.71/4 Aug, 2007- June, 2011

Bachelor of Engineering in Electronics & Communication Engineering

COURSEWORK

VLSI Design, VHDL/Verilog Design Synthesis and Verification, Mixed Signal VLSI Design, VLSI Fabrication, Computer Architecture & Design, Solid State Electronics

REFERENCES

Available upon request

Visa Status

F-1 Visa, OPT

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