VIDYA SAGAR REDDY GOPALA

Bay Area, CA +1-559-***-**** acyh83@r.postjobfree.com

acyh83@r.postjobfree.com linkedin.com/in/vidya-gopala

OBJECTIVE: Highly motivated Computer Engineer with strong background in VLSI design, verification, testing, Embedded systems design, Computer Architecture, Circuit theory and MOS device engineering; looking for a challenging position in related fields.

PROFESSIONAL SKILL SET

Languages

Matlab, PERL, VHDL, Verilog, C, Embedded C, SPICE, Tcl/tk and shell scripting, x86 and x51 Assembly

Design tools

RTL tools, Cadence Virtuoso Schematic Editor, Synopsys Galaxy Design Platform, Tetra Max

Simulation tools

ModelSim, Spectre simulator (Cadence), NC Verilog, SimVision (Cadence), VCS (Synopsys)

Synthesis tools

Synopsys Design Compiler, Xilinx Implementation Tools

Physical Verification

Calibre tool, Assura (Cadence), IC Validator (Synopsys)

Layout tools

Layout L, Layout XL (Cadence)

Operating Systems

UNIX, Linux and Windows

Other tools

LabView, Simulink, MultiSim, Electric and Magic VLSI (layout tools)

EXPERIENCE

Trainee/ Unpaid intern 2014-2015

EkLakshya VLSI R&D Centre Pvt. Ltd. (with Sankalp Semi-conductors Pvt. Ltd). As a part of Diploma I was trained on leading industry EDA tools where I learnt and worked on RTL - GDS II complete flow. Exposed to industrial work culture and the world of semiconductors. I worked and gained exposure in ASIC Design, RTL Design, Testing and verification of digital circuits, HDL, Digital Verification, Logic Design, Circuit Theory, MOS Devices, Schematic Design, Digital Chip Create and Library Create, Full Custom Design, Standard Cell Design and Characterization.

PROJECTS

Design, Verification and testing of Digital system: Designed, Simulated and Synthesized Sequential digital circuits using Synopsys VCS and Design Compiler tools and tested using TetraMax ATPG.

Design and implementation of 32-bit single cycle MIPS Processor: Developed the processor using Verilog. It is simulated using ModelSim and synthesized using Quartus 13.0.

Verilog implementation of RSA cryptography algorithm: Implemented using Verilog coding. Synthesized and Simulated using Xilinx-ISE 10.1 on Spartan 6.

A Real-time Digital Slot Machine: Developed using Quartus13.0. Developed the hardware and software modules using Qsys and Eclipse. Implemented project on Altera DE2-115 FPGA board using Verilog coding and embedded C.

CMOS Implementation of a Read-out Circuit: The Project was done using Virtuoso (Cadence). The circuit schematic was developed and a layout was implemented in 180nm technology using gpdk180 library.

24-bit Serial-in serial-out shift register: Lead and worked with the team for the successful designing of SISO. Developed Standard cells of D flip flops and Inverter. Incorporated clock tree approach for clock and reset signal distribution. Schematic design and the full custom layout design were made for the project.

Wallace Tree Multiplier: Involved in design of logic gates and implementing Wallace tree multiplier. Carried out Full custom layout, DRC, LVS checking, and parasitic extraction for the same.

8-bit Johnson Counter: Design D-Flip-flop for implementation of the counter. The full custom layout design was done using Cadence tools. Standard Cell library was also designed for the same project.

Study of PI Controller and it’s characteristics with feedback: Designed and implemented PI controllers using analog computer and comparison is made with the simulated one. Matlab, LabView and Simulink tools were used in the project.

EDUCATION

MS in Computer Engineering at CSU, Fresno, USA, CGPA = 3.84/4.0 May, 2017

B.E., Electronics and Communication from VTU, Belgaum, India, CGPA = 3.50/4.0 2011-2015

Diploma in VLSI, Eklakshya VLSI R&D Centre Pvt. Ltd., Bangalore, India. 2013-2015

Major Courses: ASIC Design, RTL Design, Testing and verification of digital circuits, HDL, Digital Verification, Logic Design, Circuit Theory, MOS Devices, Schematic Design, Digital Chip Create and Library Create, Full Custom Design, Standard Cell Design and Characterization. Low power microarchitecture design, Microprocessor(x86), Microcontroller(x51), Analog and Mixed mode VLSI Design, Low Power CMOS Design, Analog Electronic Circuits, Fault tolerant and Fault Testable hardware design, Operating Systems.

LIST OF PUBLICATIONS

Dr. Reza Raeisi., Vidya sagar reddy Gopala. Empirical Learning of Digital Systems Testing and Testable Design Using Industry-Verified Electronics Design Automation Tools in Classroom. ASEE-PSW 2017 Annual Conference. Manuscript in preparation.

Dr. Reza Raeisi., Vidya sagar reddy Gopala. A Study of Emerging Memory Technology in Hybrid Architectural Approaches of GPGPU. ASEE-PSW 2017 Annual Conference. Manuscript in preparation.

CERTIFICATIONS

Global Engineering, Beijing Language and Cultural University, China Mar 2015

Leadership and Management, MTC Global, ACT Sol & Associates Feb 2015

Machine Building and Robotics, Evobi Automations Pvt. Ltd Apr 2013

Business English Certification Preliminary, University of Cambridge Sept 2012

PERSONAL PROFILE

Accomplishments: Teaching and Instructional Student Assistant (Oct-2015 to Present), Department of Electrical and Computer Engineering, California State University, Fresno. I teach, assist in lab and grade work done by students as a part time job in the same department where I study.

Strengths: Problem solving, self-starter, Communication skills, Listening skills, Self-motivated, Self-directed, Team player.

Competition: Won the Intra-Collegiate Project Competition, COSMOS held at Christ Junior College Oct 2010

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