Resume

Sign in

Design Assistant

Location:
Tamil Nadu, India
Posted:
January 24, 2017

Contact this candidate

CURRICULUM VITAE

VISHAL GUPTA

B. E. (ECE), M. Tech. (VLSI Design)

Mobile: +91-761*******

Email: acygnx@r.postjobfree.com

Add: Darji oli, Jamdar khana, Vyas ki gali,

Lashkar, Gwalior, Madhya Pradesh, India - 474001

Career Objective:

As I completed my post-graduation in the VLSI stream, to obtain a creative and challenging position in an organization that gives me an opportunity for self-improvement and leadership, while contributing to the symbolic growth of the organization with my technical, innovative and logical skills.

Achievements:

“Young Scientist Award” by M.P. Council of Science and Technology

(MAPCOST), Govt. of M.P., Bhopal, 2016.

“Young Scientist Fellowship Award” by M.P. Council of Science and Technology

(MAPCOST), Govt. of M.P., Bhopal, 2016.

“Teaching Assistantship/Scholarship” awarded by MHRD for GATE 2013 Score.

“Gahoi Vaisya Samaj National Scholarship” awarded by Gahoi Vaisya Samiti, New Delhi.

Summary of Qualification:

Physical Analog & Digital Design, VLSI Verification and Teaching experiences.

Hands-on experience and knowledge of SRAM compiler or custom memory characterization.

Good understanding of layout design of memories & memory architectures.

Good understanding of physical verification checks DRC, LVS, PEX and ERC.

Simulations and characterization flows and tools for process nodes 45nm.

Understanding of industry standard EDA tools for the front-end design and back-end design verification.

Good knowledge in VLSI circuit design power management and Dynamic Voltage Scaling.

Good understanding of basics of CMOS circuits & design concepts for low power CMOS circuits.

VLSI Domain Skills:

HDL : Verilog, VHDL (Basics)

Physical Verification Checks : DRC, LVS, PEX, ERC

Domain : Front-end Design, Back-end Design, Memory design, Layout design, and Verification.

Knowledge : RTL Coding, FSM based design, Simulation, Synthesis, Memory architecture, Low power

circuit, Static timing analysis, CMOS, SoC.

Software Languages and EDA Skills:

Languages : Basic knowledge about C, Assembly language, VHDL and Verilog.

EDA Tools : Cadence Virtuoso IC 6.1.5.500.15,

Xilinx ISE Project Navigator (version 14.7 i)

Altera Quartus II (version 6.1).

Physical Verification Tool : Assura, Calibre.

Simulation Tools : ModelSimSE-EE5.4A, ISim, MATLAB 2008.

Embedded System Design : Keil u Vision, 8051 simulator.

Protocols : Ethernet, UART, I2C, USB.

Other Skills : CMOS Design, Digital Design, ASIC, FPGA, Embedded Systems Design and Latex.

Operating Systems : Redhat Linux, MS Windows.

Project:

1. M. Tech. Project “Modeling & Estimation of FinFET based 6T SRAM Cell Considering Process Parameter Variation”.

EDA Tool : Cadence Virtuoso (Model file 45nm).

Keywords : FinFET, Static Power dissipation, SRAM Memory Cell, Process Parameter.

Description : Minimizing the leakage power in the SRAM memory cell by using Drowsy cache implementation.

2. B. E. Project “Designed Keyboard Programmable Digital Lock Circuit”. Software & Hardware: Keil u Vision, LS7223 Micro Controller Key Word : Digital lock, Microcontoller, LCD, Keil Compiler. Description : by using LS7223 Programmable Micro Controller based on the C language programming.

3. B. E. Project “Designed a Cordless Voltage & Current Tester”. Software & Hardware: Invertor 4069.

Key Word : PCB designing, PCB Implementation, Voltage, Current. Description : Gives Facilities us to knowing the flow of voltage & current in the shield wire.

Experience:

1. Worked as a Research Scholar at ITM, Gwalior, Madhya Pradesh from August 2013 to March 2016.

Responsibilities : Research activities related to Subject and Lab conduction of undergraduate engineering students.

Subject taken : VLSI design and simulation Lab (Verilog & VHDL). 2. Worked as Assistant Professor at Chartered Institute of Technology, Abu Road, Rajasthan from July 2012 to July 2013.

Responsibilities : Teaching to engineering undergraduate students of Rajasthan technical university, Kota.

Subject Taken : Electronic Devices, Analog & Digital electronics, VLSI Design, VLSI Technology, Industrial Electronics.

Academic Qualification

1. Graduate Aptitude Test in Engineering (GATE) Qualified in 2013 & 2014. 2. Completed Masters in Technology (VLSI Design) at ITM Gwalior Affiliated to Rajeev Gandhi Proudyogiki Vishwavidyalaya, Bhopal (MP).

Thesis Work: Thesis for the award of M. Tech. on “Modeling& Estimation of FinFET based 6T SRAM Cell Considering Process Parameter Variation”, using

“Cadence Virtuoso” at 45nm node.

Major Academic Courses highlight: Verilog Design, VLSI Technology, CMOS Technology, Advanced Logic Design, Digital Electronics, Industrial Electronics. S. No. Name of Degree Discipline/Specialization % or CGPA Year of Passing 1. M. TECH. VLSI DESIGN 7.64/10.0 2016

2 B. TECH. ECE 73.00% 2012

3 XII PCM 77.00% 2007

4 X MATHS, SCIENCE 84.00% 2005

Research & Publication:

Gupta, V., Khandelwal, S., Raj, B., and Gupta, R D., (2015). Process Variability Aware Low Leakage Reliable Nano Scale DG-FinFET SRAM Cell Design Technique, Journal of Nanoelectronics and Optoelectronics, Volume 10, Number 6, p810-817 (December 2015). (SCIE LIST)

Gupta, V., Khandelwal, S., Raj, B., and Gupta, R. D., (2015).Leakage Current Reduction in FinFET based 6T SRAM Cell for Minimizing Power Dissipation in Nanoscale Memories, Fifth Nirma University International Conference on Engineering, (NUiCONE 2015), Ahmedabad, Gujarat, India, (2015). (Presented- IEEE Conference)

Gupta, V., Khandelwal, S., Raj, B., and Gupta, R D., (2015). Fin-FET based Disturbance Free SRAM Cell Design on 45nm Node with the Effect of Line Modulation, International Conference on Nanomaterials & Nanotechnology, (NANO 15), Tiruchengode, Tamil Nadu, India, (2015). (Presented- SCIE Conference)

Gupta, V., (2016). Design & Analysis of Power Reduction Micro-architectural Techniques and Circuit in FinFET based SRAM Cell, proc. of 31st M.P. Young Scientist Congress (M.P. Council of Science and Technology), p76.

Gupta, V., Khandelwal, S., Raj, B., and Gupta, R D., (2015).Nano-Scale FinFET based 6T SRAM Cell Design Analysis for Leakage Power Reduction, International Advances in Applied Physics and Material Science Congress & Exhibition (APMAS- 2016), Steigenberger Hotel Maslak, İstanbul, Turkey, (2016). (Accepted- SCIE Conference)

Workshop and Trainings:

1. 28 days Training at “Bharat Heavy Electricals Ltd., Jhansi” at the department of Telephone Exchange on the fundamentals of GSM & Networking. 2. Conduction of 10 days Industrial training As a Trainer on ATMega8 Microcontroller

“PCB, Robotics, Embedded System & Skills of Electronics” with the association of doc system, Bangalore, India.

3. Participated in 2 days workshop on “Embedded System Design” by Embby Logics. 4. Attended Workshop on “National Workshop on Emerging Trends in Material for Engineering Application” in under TEQIP-II” at Govt., “MITS” Gwalior. 5. Participated Faculty Development Program on “Circuit Simulation/ PCB Design” using Target 3001Software with “DELLSOFT” Technologies Pvt. Ltd. 6. Co-ordinated & Participated in 3 days Faculty Development Program on “Enhancing Academic Excellence through Research and Modern Pedagogy” in “CIT” Abu Road.

7. Participated in 2 days Workshop on “Robotics” in “TECHNOVATION-09”, Gwalior. 8. Participated in 2 days Workshop on “Hardware & Networking” in

“TECHNOVATION-09”, Gwalior.

Extra-Curricular Activities:

“Editor-in-chief” in College Newsletter in CIT, Abu Road.

Life time member of “The Indian Science Congress Association” (ISCA), Kolkata, India.

Efficiently coordinated Technical Event like “Robo Race”.

Achieved 1st position in “Debate Competition” at school & college level.

Achieved scholarship at school level.

Strength:

Strong analytical problem solving skills.

Willingness to learn new things.

Good team player.

Self-motivated and Smart worker.

Hobbies:

Travelling.

Meeting people.

Reading books.

Listening to music and Internet Surfing.

Personal Details:

Name : Vishal Gupta

Father's name : Rajendra Gupta

Date of Birth : 04th April, 1991

Linguistic Abilities : English, Hindi

Gender : Male

Marital Status : Single

Current Location : Gwalior (Madhya Pradesh)

Ready to relocate : Yes

References:

1. Dr. C. Loganathan

Principal, Professor

CIT, AbuRoad

Contact: +919443672390

Email: acygnx@r.postjobfree.com

2. Dr. Balwinder Raj

Assistant professor

NIT, Jhalndhar

Contact: +911812690320

Email: acygnx@r.postjobfree.com

3. Dr. Saurabh Khandelwal

Assistant professor

ITM, Gwalior

Contact: +91-971305180

Email: acygnx@r.postjobfree.com

4. Mr. Ashok Kumar

Assistant professor

CIT, AbuRoad

Contact: +91-946*******

Email: acygnx@r.postjobfree.com

Declaration:

I hereby solemnly declare that all the above facts are correct to the best of my knowledge and belief.

Date:

Place: Gwalior VISHAL GUPTA



Contact this candidate