Process Development

Semiconductor Process Development Professional R&D Scientist

HUSSIEN NILI

Phone: 805-***-**** Email: *******.****@*****.***

LinkedIn Profile: goo.gl/el5rEk

Google Scholar: goo.gl/sot01s

Address: 601 E Anapamu Street, Santa Barbara CA 93103

Objective

Semiconductor process development professional looking to employ extensive theoretical and experimental background in DOE, project management, process development and materials science in challenging engineering roles in an industry leading semiconductor company.

Professional Summary

Led multiple large interdisciplinary projects and single end-point studies; collaborated on a wide range of materials science/semiconductor process engineering projects.

Extensive technical/experimental experience in design and synthesis of material systems, micro/nano- fabrication, material and device characterization techniques, RRAM (memristive) devices synthesis and integration, and performance analysis.

Experienced (6+ years) in all stages of semiconductor process and device development. Design of experiments (DOE), materials synthesis and characterization, device layout design and fabrication, statistical process control (SPC), process and performance yield improvement.

Effective communicator with excellent interpersonal, verbal and written communication skills; and proven ability to engage external collaborators and sponsors

Strong academic credentials: Authored and co-authored 20 peer-reviewed articles in prestigious scientific journals; 10+ talks and presentations in scientific conferences. Research on multifunctional oxide memories and flexible oxide electronic has attracted significant scientific and public attention.

Independent, self-starter and highly collaborative; capable of acting in lead and collaborative capacities in cross-disciplinary projects in materials science/semiconductor process development.

Core Competencies

Design of Experiments (DOE)

Project Management

Semiconductor Process Development

Materials Characterization

Statistical Process Control (SPC)

Micro/Nano-Fabrication

Yield and Reliability Improvement

Electrical Characterization

Process Integration

Memory Devices (RRAM)

Thin Film Synthesis and Optimization

MEMS/NEMS

Flexible Electronics

Root Cause Analysis

Metrology and Defect Inspection

Testing and Benchmarking

Work Experience

Postdoctoral Scholar, 09/2015 to Current

University of California Santa Barbara – Santa Barbara, CA, USA

-Lead process design and development for bio-nanoelectronic interface platforms utilizing bio-compatible analog memristive (resistive switching) devices:

Identified and implemented materials, processes and fabrication routes for low-power bio-realistic analog memristors (as artificial synapses) within the CMOS process boundaries.

Designed and implemented a controlled nanoporous silicon processing (NP-Si) system for precise formation of sub-10nm nanoporous layers with control over reaction rate and average nanopore diameter

Developed the fabrication process for bio-compatible low-power NP-Si based multi-layered two terminal memristors from bottom-up: layout design, lithography, deposition of low-stress and roughness optimized metal electrode and barrier layers (E-beam and ALD), and design and synthesis of multi-layered thin film structure (CVD/PVD).

Conducted process yield and reliability surveys, and in-depth performance characterization studies to benchmark the performance of artificial synapses for simulated learning and neuromorphic computing applications.

-Lead the design and implementation of highly secure hardware-intrinsic security primitives based analog metal-oxide memristor (RRAM) circuits:

In-depth characterization of analog metal-oxide (TiO2-x) memristive (RRAM) devices and crossbar circuits for yield, reliability and temperature/noise-stability to benchmark their performance in hardware-intrinsic security architectures.

Coordinated research and development efforts on hardware-intrinsic security primitives based on nano-ionic memristor devices with external collaborators (pre-print draft: goo.gl/VpFiOx).

Designed and implemented highly secure hardware security architectures (physical unclonable functions: PUF) with minimal peripheral overhead based on monolithically integrated three-dimensional memristor (RRAM) crossbar circuits (pre-print draft: goo.gl/mAuXtM).

-Prepare progress reports, funding applications, publication drafts and presentations; engage and coordinate with

external collaborators and sponsors.

Honorary Associate, 09/2015 to Current

Royal Melbourne Institute of Technology – Melbourne, VIC, Australia

-Advise on and support the process development on materials science and functional materials research and

development projects:

Design and implementation of high-performance oxide-based memory, electro-optical and electro-mechanical devices.

Device performance and hardware architecture design and development of hardware-intrinsic security primitives.

Optimized PVD synthesis (sputtering, PLD) and nanostructuring of disordered transition metal-oxide thin films (VO2, MoO3, etc.) for photochromic and thermochromic platforms.

Patents, publications and funding preparations and progress reports.

Research Fellow, 03/2015 to 09/2015

Royal Melbourne Institute of Technology – Melbourne, VIC, Australia

-Led the R&D projects on CMOS compatible high-performance complex oxide memristors and multi-functional electronic devices:

Designed and developed the room-temperature fabrication process, based on a transferable flow and pressure-controlled sputtering (PVD) process, for low-power analog grade memristors (RRAMs) based on disordered perovskite oxide multilayers (a-SrTiO3 x) with superior switching properties and stability (patent pending).

Carried out extensive materials and device characterization studies to identify the origins and dynamics of ionic charge transport in nano-filamentary networks in disordered perovskite oxides and determine performance and failure root causes: temperature dependence and noise studies, stoichiometry analysis (XPS), electronic structure (PL), microstructure and nanoscale defect structure (cross-sectional HR-TEM, EDX and EELS) studies (journal paper: goo.gl/fFCn1u).

Designed and developed the fabrication process for electro-optically coupled transparent complex oxide memristors with optimized indium-tin-oxide (ITO) electrodes and interface-engineered SrTiO3-x multilayers (publication pending).

-Co-lead the R&D project on high-response paint-based piezoelectric platforms for a cost-effective unified road traffic monitoring:

Identified, procured and prepared materials, process tools, and experimental environments for the development of paint-based piezoelectric sensors.

Solved complex process problems for materials incorporation in the water-based and solvent-based paints. Determined and developed the process conditions, additive concentrations and mixing routes for incorporation of conductive and piezoelectric nanoparticles in the paint-based load and speed sensory systems.

Designed, developed, and field-tested a high-response paint-based road sensor platform with exceptional response and load-calibrated response voltage, to be employed as stand-alone sensors for traffic monitoring

-Worked with team members and external collaborators on a wide range of R&D projects; including flexible electronics (sensors and optical platforms), two-dimensional materials, surface acoustic wave (SAW) platforms, and photo/thermochromic material platforms.

-Served an advisory role for undergraduate and graduate research projects. Trained and mentored students on project development and progress, experimental procedures, and process and characterization tools operation. Attended orientation and progress meeting to provide feedback and projects and guide their progress.

PhD Researcher, 07/2011 to 02/2015

Royal Melbourne Institute of Technology – Melbourne, VIC, Australia

-Focused on process development for multi-functional complex oxide platforms (resistive switching devices, ferro/piezoelectrics, MEMS/NEMS) and the development and implementation of advanced materials characterization techniques:

Developed the first CMOS-compatible process route for high-performance and scalable nanoionics resistive switching devices based on PVD-synthesized disordered perovskite multilayers (SrTiO3 x) with excellent analog switching and reliability properties. Identified and implemented process routes for dopant incorporation towards improving the analog properties. (journal papers: goo.gl/jC9nBa, goo.gl/DS237J).

Developed an accurate nano-contact probing technique based in situ electrical nanoindentation, accounting and calibrating for surface contact area and probe geometric imperfections, capable of probing electrical transport and coupled electromechanical properties down to sub-50 nm resolutions. (journal papers: goo.gl/zbrwRB,goo.gl/VmXJcA).

Developed controlled synthesis processes for lead-free piezoelectric thin films (KxNa1-xNbO3) and nanostructures for energy harvesting applications, through PVD (sputtering) deposition and post-deposition treatment techniques; allowing for direct control over thin film stoichiometry and microstructure utilizing a single ceramic target (journal paper: goo.gl/YeJAfj).

Utilized extensive materials characterization techniques for stoichiometric and electronic structure properties (XPS, EDX, PL, EELS, etc.), microstructure (XRD, SEM, TEM), and surface and electromechanical properties (AFM, c-AFM, in situ Nanoindentation) to develop and optimize materials and devices process development.

Performed in-depth electrical and structure-property characterization to benchmark device and system performance.

-Contributed to ongoing projects in process and platform development led by other team members and external collaborators. Projects include MEMS/NEMS, flexible electronics, two-dimensional materials, thermoelectric platforms.

-Owned process and materials characterization tools (Lesker PVD, Hysitron’s TI950 Triboindenter, Agilent test stations).

Research Associate / Project Manager, 02/2010 to 06/2011

RFIC System Laboratory, University of Tehran – Tehran, Iran

Led the project on design and development of a CAD tool package for layout optimization of on-chip passive elements and interconnects:

Characterized structural-property dynamics of on-chip passive elements and element via full-Wave electromagnetic simulations (IE3D, Sonnet). Developed advanced analytical equivalent circuit models for passive elements and interconnects.

Developed of optimum heuristic synthesis algorithms based on partial equivalent circuit models and geometric programming.

Designed and implemented CAD toolboxes for different stages of analysis and optimum design of on-chip interconnects and passive elements.

Served an advisory role for undergraduate research projects.

Education

Ph.D.: Electrical and Computer Engineering (Microelectronics), 2015

Royal Melbourne Institute of Technology - Melbourne, Victoria, Australia

Dissertation: High-Performance CMOS-Compatible Perovskite Oxide Memristors Compositional Control and

Nanoscale Switching Characteristics

Bachelor of Science: Electrical and Computer Engineering (Electronics), 2010

University of Tehran - Tehran, Iran

Technical Skills

Semiconductor Process Development (Materials Synthesis and Micro/Nano-Fabrication)

Thin film synthesis and optimization: PVD (Sputtering, E-beam, Thermal Evaporation) CVD/PECVD, and Atomic Layer Deposition (ALD) for metals, oxides Electroplating.

Photolithography and patterning: Layout design resist optimization and planarization contact, projection and stepper lithography wet/plasma etch (RIE, ICP) Nanostructuring Chemical Mechanical Planarization (CMP) Wire-Bonding

Profilometry and Surface Inspection: Contact (stylus) and optical profilometer Atomic Force and Scanning Probing Microscopy (AFM, SPM) Ellipsometry Scanning Electron Microcopy (SEM)

Materials and Device Characterization

Compositional and Microstructure Analysis: X-ray Photoelectron Spectroscopy (XPS) X-ray Diffraction (XRD) Energy-Dispersive X-ray Spectroscopy (EDX) Electron Energy Loss Spectroscopy (EELS) Photoluminescence Spectroscopy (PL) Secondary Ion Mass Spectroscopy (SIMS)

Imaging, surface, and defect analysis: Scanning Electron Microcopy (SEM) High-Resolution Transmission Electron Microcopy (HR-TEM) TEM Sample Preparation Atomic Force and Scanning Probing Microscopy (AFM, SPM) Conductive AFM (c-AFM) in situ Nanoindentation

Electrical Characterization: Characterization Test-Bed (Direct Probing, Chip Inspection) Temperature Dependence and Noise Analysis Test Scripting (Agilent B1500 and Keithley SCS 4200 Interfaces) Failure Root Cause Analysis Performance Benchmarking

Software Skills:

Programming Environments: C++ MATLAB Python Visual Basic

Engineering Design and Simulation: LabView Qatan Digital Microscope (SEM/TEM Micrograph Processing and EELS Analysis) Nanoscope and Gwyddion (SPM Image Analysis) Altera Quartus and ModelSim (Digital Logic and FPGA design) Code Vision, Protel DXP and AVR Studio (Microcontroller Programming) HSPICE (Circuit Simulations) COMSOL Multiphysics (FEA Analysis) Sonnet EM (Full-Wave EM Simulations)

Miscellaneous: MS Office Suite Latex Linux SketchUp PhotoStudio CorelDraw ImageJ

Contact this candidate