Manager Project, Soccer and Badminton

Swee-Hing Wong

Cupertino, CA ***** • 408-***-**** • ************@*****.***

PROFESSIONAL SUMMARY

I am looking for an opportunity in chip design and development lead role that could utilize my expertise and soft skill as follow:

• 20 years of semiconductor IC design, testing and project management experience, in which more than 10 years of technical hands on design experience in various types of circuit/block and memory/IP, plus another 10 years of project management and leadership experience.

• Familiar with design, silicon validation and test/qualification methodologies/tools/flows. Been through most of the phases with actual hands on experience in different types of product, such as CPU, Chip set, SoC, ASIC and NPU.

• Good team player or leader with good communication skill and plenty of cross functional, company, country/cultural working experience. EXPERIENCE

Intel Corp. (Foundry, Santa Clara) 12/2012 – 05/2015 Director, Program manager (resigned to take care of personal matters for 6 months)

• Program manager of a few foundry products (22nm & 14nm). The primary customer facing person and internal lead for driving and coordinating technical support.

• Responsible for providing training, design, technology, manufacturing, test support and collateral to customers to ensure project success from design start to QUAL/PRQ.

• Had taped-out and enabled productions of multiple customer product (ASIC and COT). Intel Corp. (Chip Set, Santa Clara) 5/2011 – 11/2012 Project manager & I/O circuit design manager

• Project manager responsible for delivering completed integrated IO Ring design/solution chip set products, such as Lynx Point (32nm) and SunRise Point

(22nm).

• Lead a team of 10 ckt designers to develop special circuit blocks/IPs such as SRAM/RF, VR/LDO, Fuse, CLK/PLL for chip set products.

• Work closely with other stakeholders, including other IP providers, Front-end design and Full Chip integration teams to successfully taped-out and tested/productized multiple products.

Intel Corp. (Embedded SoC, Penang) 4/2006 – 4/2011 Director of Silicon Engineering

• Led and managed a team of 130 Design Engineers and Product Development / Test Engineers.

• Owner of the design and development of the following products from product definition, design implementation, Silicon debug to product qualification (PRQ):

• IXP430 series: Xscale based SoC on .13um. Network processor

• E600 series: Atom based SoC on 45nm. First embedded IA SoC at Intel

• Rose Point: Atom based SoC on 32nm. – Cancelled after A0 stepping due to market direction changed.

Intel Corp. (NPU, Penang) 6/2002 – 3/2006

Project Manager and Design Lead.

• Project Manager of IXP430 (NPU SoC). Led project from product definition to design taped out and silicon debug complete. (May 2004 – Mar 2006)

• Design team lead/manager of IXP2350 project, in charge of clock, fuse, memory, power, reliability and timing closure (Jun 2002 – May 2004) Procket Networks Inc. (ASIC, Milpitas) 3/2001 – 6/2002 Member of Technical Staff

• Implemented cell base custom ASIC design flow by manually coding gate level Verilog and physical cell placement using in-house tools.

• Participated in entire physical design flow starting from early feasibility study, floor planning, power/clock planning, implementation and tape-out, followed by system level debug for NPU and MCU products.

• Involved in DLL circuit design, performed signal integrity checks, simulations and measurements during HW bring up.

Intel Corp. (CPU, Santa Clara) 5/1995 – 3/2001

Sr. Circuit Design Engineer - Member of Staff

• Itanium ®:

• Supervised a team of 6 engineers and 4 mask designers, with extensive hand on planning and design experience.

• Strong technical background and expertise in every circuit/physical design and verification aspect, such as memory design, dynamic circuit, data-path, crosstalk, timing and formal verification.

• Involved in silicon debug on Itanium ® A0 and B0.

• Pentium ® II (Klamath)

• Responsible for delivering physical design of 2 functional blocks in SIMD unit. EDUCATION

MSEE of Syracuse University, Syracuse New York, USA (Sept 1993 – Dec 1994) BSEE of National Tsing Hua University, Hsin Chu, Taiwan (Sept 1986 – Jun 1990)

Contact this candidate