PRATHIBA SRINIVAS

**** ********* ****, #****, ******, TX 78735

Email: acy7sr@r.postjobfree.com, Mobile: +1-469-***-**** Objective

To obtain a challenging position starting March 2017 in the field of Electrical Engineering. Education

Master of Science in Electrical Engineering, GPA 3.52/4.0 Jan 2015 - Dec 2016 The University of Texas at Dallas, Richardson, TX

Bachelor of Engineering in Electrical Engineering, Percent 82% Aug 2010 - May 2014 Reva Institute of Technology, Karnataka, India

Skills

Programming Languages : Verilog, Assembly, RTL, SystemVerilog (UVM), VHDL, Perl, Shell, C, C++ CAD tools and simulators : Cadence Virtuoso, Spectre, Assura, HSPICE, Modelsim, Xilinx Physical Design tools : Synopsys Design Vision, Cadence SOC Encounter, Synopsys IC Compiler Static timing analysis : Primetime

Relevant courses

VLSI Design ASIC Design Design Automation of VLSI systems Advanced VLSI Design Computer Architecture Microprocessor Systems Design for test ( DFT) Advanced Logic Design Hardware Description Languages Work Experience

Design Intern, Indian Institute of Science, Karnataka, India Jan 2014-Dec 2014

• Designed a Low Power ASIC chip embedded on a Walking stick that assists the aged with poor vision to navigate easily without any physical obstruction.

• Implemented obstacle detection system at structural level and performed physical design in IC Complier.

• Optimized the chip for minimum area, power and timing.

• Functionality of the chip was tested using RTL simulations. Academic Projects

ASIC Design - A Low-Power Mini Stereo Digital Audio Processor (MSDAP) Fall 2016

• Designed an ASIC chip to implement a digital FIR filter capable of performing audio processing functions.

• Behavioral and RTL codes were written in Verilog and synthesis was performed using Design Vision.

• Performed floor planning, place and route, power and timing analysis using Synopsys IC Compiler. Design and layout of a 256 x 8bit 8T memory cell based SRAM using the IBM 130nm process Sum’ 2015

• Designed a Dual port, 2Kb SRAM using 8T Memory Cells with interface circuits, row & column decoders, pre-charge circuit and sense amplifier to achieve low power.

Implemented Logical effort in sizing the transistors for row and column decoders. Layout of the entire design was done manually using Cadence Virtuoso along with DRC, LVS checks.

Performed post layout simulation using HSPICE & WaveView by extracting the spice model of the design. RTL Design and UVM Verification - Reverse Engineered ARM CPU (RISC) Fall 2016

• Developed an RTL level code for limited instruction set ARM architecture with ALU, Decoder, Registers, Program counter, Instruction Registers and Memory modules for 32-bit instruction set in Verilog.

• Designed a complete UVM testbench with environment, generator, driver, scoreboard, monitor and checker classes using Transaction level modeling.

• Constrained-random stimulus was generated and tested within the UVM environment. Computer Architecture - Cache Design Optimization Fall 2015

• Optimized the cache hierarchy of an Alpha 21264/EV6 microprocessor for three different benchmarks by fine-tuning cache design parameters like cache levels, block size, associativity and block replacement policy using SimpleScalar-3.0 simulator.

• Wrote a Perl script to automate the fine-tuning of design parameters process.

• Cost function was defined to identify the optimal configuration. Fault Simulation, Test Pattern generation, DFT and BIST implementation Spring 2016

• Designed and synthesized digital circuits using Synopsys, realizing stuck-at-faults and transition faults, generating test vectors, ATPG, reported test and fault coverage using Synopsys Tetramax.

• Fault collapsing, test pattern generation for combinational circuits and comparing results with ATPG.

• Realized Scan compression using Synopsys DFTMAX tool and boundary scan (JTAG) using the BSD tool.

• Implemented Linear Feedback Shift register and Multiple Input Signature register for specific polynomials that acts as pattern generator and response compactor in BIST circuit. Bi-Partitioning of Netlists using Simulated Annealing Algorithm in C Fall 2015

• Implemented an algorithm for Bi-Partitioning of Net-lists using Simulated Annealing approach in C.

• The net-list files used to test the algorithm were from the ISPD98 Circuit Benchmark Suite.

• The net-list and area files were parsed and simulated annealing based algorithm was implemented in C to get two equal sized partitions with minimum number of nets connecting them (minimum cut).

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