Engineer Project

GIRIJA BAGALI

LIC Colony,

Bangalore-******

Phone: +91-973*******.

E-mail: acxzr4@r.postjobfree.com

Personal details:

Name : Girija Bagali

Date of Birth : 13/11/1991

Languages known : English, Kannada, Hindi

Career Objective:

Seek a challenging career in a technical field where my personal goals can be integrated in the organization that provides me the exposure to the cutting edge of technology and my abilities can be used for the company's benefit and help me improve myself.

Experience:

Organization

Designation

Duration

CORI,R&D Center Bangalore

Intern( Research Associate)

March 2016 - June 2016

QualOrbis Technologies Pvt Ltd

Design Verification Engineer Trainee

September 2016 - Present

Educational Qualifications:

Year/Exam Year/ Exam

Percentage

Result

Name of Institute

Name of Board

2014-2016

MTech

8.98(CGPA)

FCD

PES University, Bangalore

PES University, Bangalore

2009-2013

BE

74%

FCD

BLDEA’s College of Engineering & Technology

Bijapur

Visvesvaraya Technological University, Belgaum

2007-2009

PUC II

79%

FCD

Shri Manjunatheshwara Pre-University Science College. Dharwad

Department of Pre-University Education, Bangalore.

2007

SSLC

87.36%

FCD

Shree Mahanteshwar Vidya Vardhak Sangha,Afzalpur

Dist:Gulbarga

Karnataka Secondary Education Examination Board, Bangalore.

Skill set:

Programming languages: Verilog, VHDL, C, Matlab, SystemVerilog.

Operating System: Windows 7/ XP/8/10, Linux, Ubuntu.

Tools: Cadence, Modelsim (Mentor graphics), Simulink, QuestaSim, Xilinx.

Area of Interest: Logic Design, Digital Electronics, Basic Electronics, Microprocessor.

Project Undertaken:

M.Tech final year

Title: Implementation of Finite Field (Galois field) multiplier for ECC application.

Tool: Xilinx 14.5, Questasim 10.c.

Description:

In this project we review an algorithm of novel recursive decomposition for RB multiplication to achieve higher throughput for digit-serial implementation (PSFG).

Implementation of ECC (elliptic curve cryptography) over the Galois field.

Engineering Major Project

Team size:4

Title: Performance Improvement in Wi-MAX Networks with Femtocells

Software’s used: MATLAB7.9.

Description:

Femto cell network model that is suitable for evaluating the CINR improvement when femto cell base stations are deployed in a Wi-MAX network.

The major benefit of deploying femtocells is in its improvement of the indoor users CINR to the 50-60dB range. As more femtocells are deployed, more indoor users connect to the femtocell instead of the macro cell, greatly increasing the average CINR

M.Tech 1st Semester

Title: Implementation of MAC Unit using Reversible Logic (4 & 8 Bit)

Language & Tool: VHDL& Xilinx.

Description:

MAC (4&8bit) unit is designed for basic Arithmetic units and implementation of reversible logic.

This project presents the primitive reversible gates and which are gathered from literature and this project helps researchers/designers in designing higher complex circuits using reversible gates.

M.Tech 2nd Semester

Title: Bound solvers for filter design.

Tool: MATLAB 7.9

Description:

In this project we review two existing algorithms for determination of the iteration bound.

The two algorithms are longest path matrix algorithm and minimum mean cycle algorithm and even compared the algorithms by calculating execution times.

Positions and Responsibilities:

Working as Verification Engineer in Watchdog Timer Project and completed APB verification.

Organized an event called GANITIDEEPINI (a mathematics quiz event).

Participated in IT BILTZ quiz competition organized in Gulbarga.

Presented paper in national level paper presentation event on BLUE BRAIN.

DECLARATION

I hereby declare that the information furnished above is true to the best of my knowledge. I am also confident of my ability to work in a team.

Place: Bangalore

(GIRIJA BAGALI)

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