ASIC Design Engineer

ABDUL ROSHAN SHAIK PH: 480-***-****

**** ********* *****, #****, ******, CA 95630. Email: acxzax@r.postjobfree.com SUMMARY Graduate student applying for Full time position in the areas of Digital VLSI circuit design, RTL design and Verification, Physical Design, Component Design, ASIC Design/Verification and Design Automation. Have strong background of digital design and testing. Project experience working with the EDA tools for synthesis, APR & Static Timing Analysis, the Cadence Tools suite and functional verification using Verilog.

EDUCATION

Master of Science – Electrical Engineering May 2016 Arizona State University – Tempe, Arizona GPA: 3.32/4.0

Bachelor of Engineering – Electronics & Communication May 2014 Vellore Institute of Technology University – Vellore, India GPA: 8.16/10 WORK EXPERIENCE Scalable Systems Research Labs Inc. (August 2016 – Present)

Working as an ASIC Engineer on the design of a CONVOLUTIONAL NEURAL NETWORK COPROCESSOR, in which I am involved with writing Verilog for the CNN core and performing Functional Verification of the code, which is in turn part of a large project whose end goal is vision analysis for automobiles. SKILLS

RTL to GDSII ASIC Design Flow. RTL/Synthesis/Automatic Place and Route using SoC Encounter. STA using Primetime.

Design Flow Automation using TCL.

Experience in custom digital circuits design, Standard Cell Design, Layout, DRC, LVS, Characterization and Abstract generation.

Tools: Cadence Virtuoso, SoC Encounter, ModelSim, Hspice, Primetime, Star RC, RTL compiler, MATLAB, Synphony Model Compiler

Programming skills- C, C++, Basic PERL, Verilog, System Verilog, Shell scripting, Experience working on LINUX OS. PROJECTS

Convolution and Max Pooling Design Fall 2015

Wrote Verilog for Convolution and Max pooling for input of 512x512 image with a convolution kernel of 3x3. Optimization using parallelism, synthesized using RTL. Created Layout using SoC encounter. Identified and debugged Routing problems, cleared DRC and LVS. Measured the total area of layout, power consumption, delay, energy of final post layout circuit.

Design of a 16 bit on chip Router Fall 2015

An on chip router which is used to build the Network on chip is designed. The crossbar implementation of the router in three pipeline stages is designed and tested using system Verilog. This design is then synthesized using Encounter and then imported into cadence virtuoso and tested for DRC and LVS.

Asynchronous FIFO RTL Design & Verification Fall 2015 Designed Asynchronous FIFO in Verilog with write clock operating at 100 MHz & read at 10 MHz, implemented a self- checking Layered Testbench in Verilog to test FIFO functionality; targeted Corner cases.

32x32 Custom Register File Design Fall 2015

A one bit register cell was designed and tested for functionality and the 32x32 RF cell design was implemented in virtuoso with a shared diffusion technique. The netlist of the 32x32 RF cell layout was extracted and the worst case delays were measured

Hardware Accelerator for Radix-2 FFT using FPGA Spring 2016 Designed and verified architecture for conventional FFT in Synphony Model Compiler, implemented a new architecture for FFT using Resource Sharing keeping in mind Power Reduction and Area Efficiency. Verified the new architecture and compared Power, Area and Resource Utilization with conventional architecture using SynplifyPro.

Standard cell library design using 32nm process PDK Spring 2015 Designed standard cells of combinational gates & sequential circuits (NAND, NOR, AOI, DFF, etc). Learning outcome was a thorough knowledge on performing DRC, LVS and StarRC extraction in Hercules. Generated Abstract views, Verilog Views

& LEF (Library Exchange Format) files for the cells in the library.

Design of 8 bit modulo adder Spring 2015

Designed and simulated schematics and layout of both one-bit full adder and D flip flop in cadence virtuoso schematic editor, layout editor and HSPICE Integrated all the adders and D- flip flop layouts to form 8 bit modulo adder. Measured the total area of layout, power consumption, delay, energy of final post layout circuit.

Delay optimization and Implementation of a logic path Spring 2015 All the gates in the logic path are implemented with complementary logic and PMOS and NMOS are appropriately sized. The layout of basic gates and the entire path is generated. The delay of the path is measured using HSPICE.

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