MUSTAFA PARLAK

Address: **** ****** ***** **. ***************, VA, 22911

E-mail: mustafaparlak(at)gmail.com

Mobile: +1-434-***-****

Web: http://koclab.cs.ucsb.edu/people.html#parlak

LinkedIn: https://www.linkedin.com/in/mustafa-parlak-51367215

Self motivated digital design engineer with expertise in each design step from system level specs to RTL coding, verification and implementation. Areas of expertise include hardware implementation of video/image processing (H.264 video codec), and cryptographic algorithms/schemes.

EXPERIENCE

University of California Santa Barbara, Visiting Scholar

Jun 2015 – Present

Low power cryptographic hardware design through RTL-level optimizations running on FPGAs

Power consumption estimation of RTL modules with Xilinx Vivado, and actual power measurement on Xilinx KC705 board through PMBUS

Power characterization of Ring Oscillator based True Random Number Generators

Evaluation of cryptographic algorithms in terms of a new design metric incorporating effects of throughput, area and special focus on power.

Design/implementation of two best known modular multiplication algorithms (Montgomery and interleaved) of large numbers (> 128 bit) targeting Xilinx Kintex 7

Power estimation and measurement of modular multiplication algorithms for evaluation and comparison.

National Research Institute of Electronics and Cryptology, Turkey

Jan 2010 – Jun 2015

National Secure IP Phone, Senior FPGA Design Engineer Jan 2013 – Jun 2015

Designed SPI and UART bus driver in Verilog RTL and implemented on Xilinx Spartan-6 FPGA.

Established SPI bus connection between TI's OMAP processor and Xilinx Spartan-6 FPGA and successfully transferred data.

Designed/Implemented ring oscillator based random number generator on Xilinx Spartan-6 FPGA.

Implemented/Developed mathematical routines for NIST prime elliptic curves in MATLAB including elliptic curve multiplication, addition, doubling, and inversion, hash functions.

Written, simulated and implemented various cryptographic modules from scratch including FIPS SHA-384/512, 512/384-bit modular multiplication and modular inversion modules in Verilog HDL and implemented on Xilinx Spartan-6.

Random Number Generator, Senior FPGA Design Engineer Oct 2014 – Jan 2015

Designed simulated, and implemented statistical online tests including Frequency, Poker, Runs and Long Runs tests on MicroSemi Igloo FPGA.

Implemented/Developed MATLAB model of AES128/256 and generated test vectors from it for functional verification.

Designed and implemented AES-128 and noise processing function in Verilog RTL on MicroSemi Igloo FPGA.

Integration of Microsemi UART IP into RNG module to communicate with TI's OMAP processor.

Secure Air Combat Maneuvering Instrumentation (ACMI)

POD Communication, Senior FPGA Design Engineer Oct 2013 – Feb 2014

Probed the internal data communication inside an ACMI POD (between processor and RF module) to capture and identify the digital signals using scope.

Designed a proof of concept constant-key cryptographic system running on Xilinx Spartan-3 FPGA in Verilog HDL to extract and encrypt/decrypt the data traffic between communicating two ACMI PODs.

The communication from processor intercepted, encrypted and send to RF Module. Also backward traffic is decrypted.

Successfully tested the constant-key cryptographic system running on real ACMI POD devices communicating with each other.

Secure National Mobile Phone, FPGA Design Engineer Mar 2012 – Jan 2013

Designed and implemented symmetric-key (AES-256) encryption/decryption cryptographic system on MicroSemi (Actel) Igloo FPGA.

FPGA encrypts/decrypts voice/data traffic between TI's DSP and OMAP

Designed/Implemented various cryptographic and serial bus driver modules including ring oscillator based random number generator (RNG), AES-256, SPI and UART all in Verilog HDL

Configured bus connectivity to OMAP and DSP through SPI and UART

Power-Line Communication Modem, Embd. Dev. Engineer Jan 2010 – Mar 2012

Ported ITU G722.2 speech codec onto TI C5509 fixed-point DSP.

Integrated the G722.2 speech codec into power line modem running on TI 5509 fixed point DSP

Developed ARM Cortex-M (STM32) based user interface and communication peripherals firmware (managing input entry from key-pad, deriving dot-matrix LCD controller, managing connectivity between computer and modem through UART)

Developed firmware for data transfer between TI 5509 DSP and STM32 ARM Cortex M3 using SPI and I2C peripherals

Prepared project technical documents including progress reports, final report and technical requirement documents.

Georgia Institute of Technology, Atlanta, Postdoctoral Researcher

May 2009 – Nov 2009

Written video enhancement algorithms (color correction and sharpening of video frames) at RTL level and implemented on FPGA platform.

Sabanci University, Istanbul, Turkey, Research Assistant

Feb 2005 – May 2009

Low Power H.264 Video Encoder Design

Design and implementation of H.264 intra prediction, H.264 intra mode decision, H.264 half-pel interpolation H.264 Deblocking filter modules all in Verilog HDL

Implemented MATLAB model of H.264 Deblocking filter, intra mode decision, and intra prediction to generate test vectors used in functional verification of RTL modules

Power estimation and measurement of H.264 encoder modules running on Xilinx Virtex-II FPGA.

Estimation is performed using Xilinx Xpower

Measurement is done through FPGA power supply current reading with a multimeter.

Implementation of H.264 Deblocking Filter on Xilinx Virtex-II FPGA with bit-to-bit exactness verification of H.264/AVC JM reference software model

H.264 intra-coder implementation running on Xilinx Virtex-II FPGA of Arm development board

Integration of VGA controller in to SPARTAN-3 starter kit supplied from Digilent to display frames on VGA LCD monitor

Sabanci University, Istanbul, Turkey, Teaching Assistant

Sep 2001 – Feb 2007

Assisted in various courses including VLSI System Design, Hardware Description Languages, Microcomputer Based System Design, Analog Integrated Circuits, Digital Integrated Circuits and Electronic Circuits.

Implementation of gate-level Serial Fault Simulation tool in C.

DC-DC converter analog IC design. The design includes Reference Voltage Generator, High Performance Comparator, and PWM Modulator.

Full custom layout and characterization of Mechanically Coupled MicroElectroMechanical (MEM) filters using MEMCAD.

Full custom layout of 16-bit adders (CS, CSK, CLA, RPL) using standard cell-library of AMS 0.35u CMOS technology in Cadence EDA tools.

EDUCATION

Ph.D. in Electrical and Electronics Engineering

2003 – 2009

Sabanci University, Istanbul, Turkey

Thesis Title: "Low Power H.264 Video Compression Hardware Designs"

M.Sc. in Electrical and Electronics Engineering

2001 – 2003

Sabanci University, Istanbul, Turkey

Thesis Title: "Design and Simulation of Micro Resonator Oscillator for Communication Circuits"

B.S. in Electrical and Electronics Engineering

1996 – 2001

Middle East Technical University, Ankara, Turkey

SKILL SETS

FPGA/Digital Design, Embedded Design, Signal Processing

Experience in digital design at each step from defining the architecture at system level to RTL coding and verification

FPGA programming using Verilog HDL, experience on Xilinx and MicroSemi (formerly Actel) FPGAs

DSP software development on TI C55x series

Embedded software development on STM32 ARM Cortex-M3

Signal processing algorithm implementations in MATLAB

Expertise with Laboratory Equipment

Oscilloscope, Function Generator, Multimeter, Logic Analyzer, Impedance Analyzer, Spectrum Analyzer, Power Analyzer

CAD/EDA Software

Mentor Graphics (ModelSim, Precision RTL), Synopsys (Design Compiler), Cadence (Digital and Analog IC IDE), Xilinx ISE/Vivado, MicroSemi (Actel) LiberoSoC, TI Code Composer Studio, Keil uVision

Programming/HDL Languages

Verilog HDL, C, PASCAL

Other Software Tools

Microsoft Office, MATLAB

TECHNICAL TRAININGS

Xilinx The Programmable Logic Training Course (PLC2) "Spartan-6/Virtex 6" Jun 2010

Xilinx The Programmable Logic Training Course (PLC2) "Professional DSP" Apr 2010

HONORS & AWARDS

Dr. Gursel Sonmez Research Award, Sabanci University, Istanbul, Turkey, Jun 2009

International post-doctoral research fellowship supported by Scientific and Technological Research Council of Turkey (TUBITAK), May 2009 - Dec 2009

Best paper in adaptive and reconfigurable circuits for multimedia in NASA/ESA Conference on Adaptive Hardware and Systems, Edinburgh, UK, August 2007

Teaching and Research Assistantship awarded by Sabanci University (Full tuition and a stipend) Sep 2001- Apr 2009

Merit based scholarship from Sabanci Holding, 1996-2001

PUBLICATIONS

Y. Adıbelli, M. Parlak, and İ. Hamzaoğlu. Computation and power reduction techniques for H.264 intra prediction. Microprocessors and Microsystems, Embedded Hardware Design, Vol. 36, No. 3, pages 205-214, May 2012.

Y. Adıbelli, M. Parlak, and İ. Hamzaoğlu. A novel energy reduction technique For H.264 intra mode decision. 18th IEEE International Conference on Image Processing (ICIP), pages 385-388, Brussels, Belgium, September 2011.

Y. Adıbelli, M. Parlak, and İ. Hamzaoğlu. Computation and energy reduction techniques for H.264 deblocking filter hardware. IEEE Transactions on Consumer Electronics, Vol 57, No. 3, pages 1399-1407, August 2011.

Y. Adıbelli, M. Parlak, and İ. Hamzaoğlu. A computation and power reduction technique for H.264 intra prediction. 13th Euromicro Conference on Digital System Design, pages 753-760, Lille, France, September 2010.

Y. Adıbelli, M. Parlak, and İ. Hamzaoğlu. Pixel similarity based computation and power reduction technique for H.264 intra prediction. 20th International Conference on Field Programmable Logic and Applications, pages 171-174, Milano Italy, August 2010.

Y. Adıbelli, M. Parlak, and İ. Hamzaoğlu. Pixel similarity based computation and power reduction technique for H.264 intra prediction. IEEE Transactions on Consumer Electronics, Vol. 56, No. 2, pages 1079-1087, May 2010.

M. Parlak, Y. Adıbelli, and İ. Hamzaoğlu. A novel computational complexity and power reduction technique for H.264 intra prediction. IEEE Transactions on Consumer Electronics, Vol. 54, No. 4, pages 2006-2014, November 2008.

M. Parlak and İ. Hamzaoğlu. Low power H.264 deblocking filter hardware implementations. IEEE Transactions on Consumer Electronics, Vol. 54, No. 2, pages 808-816, May 2008.

M. Parlak and İ. Hamzaoğlu. A low power implementation of H.264 adaptive deblocking filter algorithm. Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS), pages 127-133, Edinburgh, Scotland, August 2007.

M. Parlak and İ. Hamzaoğlu. An efficient hardware architecture for H.264 adaptive deblocking filter algorithm. First NASA/ESA Conference on Adaptive Hardware and Systems (AHS)), pages 381-385, Istanbul, Turkey, June 2006.

Y. Gürbüz, M. Parlak, T. F. Bechteler, and A. Bozkurt. An analytical design methodology for MicroElectroMechanical (MEM) filters. Sensors and Actuators A: Physical, Vol. 119, No. 1, pages 38-47, March 2005.

Y. Adıbelli, M. Parlak, and İ. Hamzaoğlu. A computation and energy reduction technique for H.264 deblocking filter hardware. IEEE 19th Conference on Signal Processing and Communications Applications (SIU), pages 210-213, Antalya Turkey, April 2011 (In Turkish).

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