Baljit Chandhoke acxrlf@r.postjobfree.com 650-***-**** San Jose, CA

Field Application Engineer

Business Development Product Definition Field Applications System Applications Digital Analog

Amplifiers 10/100 Gbps Ethernet SFP+ Transceivers Competitive Analysis RF Mixers VGA’s Fiber Optics PHYs ADC DAC EPON/ GPON SerDes PLLs XOs Clocks RF WiFi ASIC Networking Standards Telecom Video CA TV Base Stations Signal Integrity High Speed Data Communications

Innovative, strategy-driven Field Application Engineer with 15 years of experience in customer facing roles within the semiconductor industry driving high-impact initiatives for global companies. Extensive collaboration with customers with onsite meetings world-wide to understand current system challenges and needs, drive design wins, debug customer systems, schematic reviews, lay-out reviews, define new leading edge products for consumer, networking, computing, wireless applications. Reputed as an articulate, cross-functional communicator and presenter with a solid understanding of business needs, technical capabilities and authored multiple articles, youtube videos and webinars.

Executive Education - Managing Teams for Innovation and Success Stanford – Palo Alto, CA 2014

M.B.A. (GPA: 3.9/4.0) Arizona State University – Tempe, AZ 2009

M.S., Telecommunication (GPA: 3.9/4.0) University of Colorado – Boulder, CO 2003

B.E., Electronics and Telecommunications University of Mumbai – Mumbai, India 2000

PROFESSIONAL EXPERIENCE

Product Marketing Manager Integrated Device Technology (IDT) Sept. 2011 – Present

Interfacing with customers worldwide defining new products, competitive benchmarking, driving design wins, product presentations, creating applications & marketing collateral, and world-wide product launches. Trained field applications engineers (FAEs) and regional sales force and demonstrated products in trade shows.

Led technical support of IDT new products supporting key strategic customers world-wide (Tier 1s), authored datasheets, marketing requirement documents (MRDs), application notes, articles.

Created Account penetration strategies for focused accounts and go-to-expert for IDT new products targeting Networking (10G/100G Ethernet, Data Centers), Wireless, Consumer, Industrial, Video & Data Communications market segment.

Successfully launched PLL Clock sythesizers, RF PLLs, RF Switches, Digital Step Attenuators, Mixers, Variable Gain Amplifiers and managed the product roadmap, business plans and go-to market strategy.

Product Line Manager for the integration of Fox XpressO crystal oscillators into IDT XU and XL Family of crystal oscillators and the worldwide launch of the IDT XO’s.

Led the cross functional team in the product definition, C-level buy-in, design execution and Launch of new Buffer Base with 20 products launched in the fastest new product introduction from concept to launch within 1 year. Buffer products gaining traction with over $15M in design in opportunity funnel & $5M in DINs.

Won the Annual Creativity in Electronics (ACE) Award for VersaClock 5 Family which is the most successful new timing product at IDT with over 300 Design Ins and $30M in DINs, $12M in DWIN in the first 18 months since introduction and additional $70M design in opportunity funnel. Achieved $5M in revenue within 2 years of product family launch with 15 new products introduced in the VersaClock 5 Family.

Gained mindshare from World-wide sales force by customer visits, driving new timing and RF products customer adoption, training distribution, IDT Sales and FAE’s. Followed up weekly & monthly on opportunities, sales pipeline, pricing and sampling to drive DINs and DWINs. Presented at Avnet, EBV FAE Conference and showcased IDT products at Embedded World, EDI CON, IMS Trade Shows.

Authored 12 technology articles published in industry leading publications – EE Times, EDN, Embedded, 10 YouTube videos and EE Web & Microwave Journal Webinars demonstrating leadership position of IDT in timing and RF products.

Principal Application Engineer ON Semiconductor Aug. 2006 – Sept 2011

Collaborated with key strategic customers and System Engineers to define new product requirements, presented business cases for management approval, and steered new product development. Increased revenue by working closely with key customers to define new Analog, Mixed-Signal, Phase Locked Loop (PLL) clocks and data management products for game consoles, digital TV, networking, consumer applications.

Led development of mixed signal ASIC for a leading networking company from China, with revenue of $6M over three years. Conducted on-site meetings in Shanghai, drove spec requirements, integrated digital-to-analog converter (DAC), watchdog, multi-PLL, I2C control, LVPECL, LVDS, LVCMOS clock outputs with sub 1 psec jitter in a mixed signal ASIC with $300K NRE in base station application.

Boosted design wins by providing technical support, evaluation board design, and responsible for $3M in revenue working with a key US cell phone manufacturer by defining and developing new analog product with an LDO (low-dropout regulator) for cell phones, saving board space, lowering power consumption.

Enabled a key US based game console manufacturer to offer a low cost solution with board space reduction by defining and developing new product, taking the USB start of frame pulse as an input and providing 12.288 MHz dual clock outputs for two audio CODECs. Achieved distinction with annual revenue of $2.5M.

Managed continuous engagement with a key networking company for 3+ years to design 10 products in a router, resulting in $1M/year in shipments and being recognized as a preferred supplier.

Improved communication throughout customer design-in and new product development process, which involved continuous customer engagement, schematic reviews, lay-out reviews, board level trouble shooting, visiting customers in sales territories worldwide and conducting trainings, webcasts for customers and FAE’s.

Senior Applications Engineer, Technical Lead Cypress Semiconductor June 2003 – Aug. 2006

Directed cross-functional video equalizer team tasked with concept-to-production new product development, including product definition, customer engagement, lab evaluation, and design verification. Interfaced with customers to design in Cypress 1.5 Gbps PHY’s (HOTLink II) and video equalizers. Led lab characterization of equalizer and SerDes with understanding of 8B/10 encoding.

Achieved return loss requirements for video equalizers via innovative high-speed evaluation board design.

Instructed Field Applications Engineers through high speed signal integrity training including thorough demonstrations of terminations, transmission lines, and impedance matching.

Demonstrated cypress video equalizer and high speed Serializers/Deserializers at domestic and international video trade shows, as well as Cypress financial analyst conference.

Electrical Engineer (Co-Op Position) Infineon Technologies Jan. 2002 – June 2003

Designed, laid out, and evaluated multiple transceivers. Collaborated with semiconductor IC manufacturers to overcome new product requirement challenges and meet Ethernet Passive Optical Networks (EPON) standards.

Designed a point-to-multipoint SFP/SFF transceiver for EPON to have a transmitter turn-on time of 600 nsec and receiver response time of 400 nsec.

Developed a bi-directional transceiver for converting optical signal to electrical signal and vice versa for transmission over optic fiber (at data rate of 155 Mbps and 1.25 Gbps).

RF Engineer (Co-Op Position) Trimble Navigation Ltd. May 2001 – Dec. 2001

Designed a frequency hopping GPS radio receiver. Completed Board Design and Validation.

Achieved 500 usec settling time and completed the design from inception within 4 months.

CONTINUING EDUCATION WORKSHOPS:

High Speed Digital Design (Signal Integrity) – Dr. Howard Johnson

Maximizing Your Leadership Potential (Course by CCL)

Collaborative Negotiations Professional Selling Skills Professional Sales Presentation

Presentation Skills Getting Things Done Across Organizational Borders

Managing Time & Multiple Priorities Precision Questioning and Answering (PQ&A)

PUBLICATIONS & WEBCASTS

Chandhoke, B. (2016). EE Web Webinar- RF Technical Innovations

https://www.youtube.com/watch?v=69xmS9uAVF8

Chandhoke, B. (2016). Programmable clocks simplify embedded multiprocessor designs, improve performance http://www.newelectronics.co.uk/electronics-technology/multiple-output-programmable-clocks-simplify-embedded-multiprocessor-designs-improve-performance-and-reduce-cost/112407/

Chandhoke, B. (2016). EBV FAE Training Demonstration

https://www.youtube.com/watch?v=p-oQVuR8_5Y

Chandhoke, B. (2016). Microwave Journal Live Webinar- Improving Base Station Design

http://www.microwavejournal.com/events/1527-improving-base-station-design-rf-innovations

Chandhoke, B. (2015). Managing the Jitter vs Power Tradeoff in Clock Trees

http://www.embedded.com/design/real-time-and-performance/4440151/3/Managing-the-jitter-vs-power-tradeoff-in-clock-trees

Chandhoke, B. (2015). Jitter Considerations when matching timing solutions to your applications

http://www.embedded.com/design/debug-and-optimization/4439793/Jitter-considerations-when-matching-timing-solutions-to-your-applications--

Chandhoke, B. (2015). Simplify System Clocking with Programmable Multi-Output Clock Generators

http://electronicdesign.com/digital-ics/simplify-system-clocking-programmable-multi-output-clock-generators

Chandhoke, B. (2014). Interview with Electronic Design on Timing Solutions

http://etn.se/images/expert/IDT_programmerbara_klocklosningar.pdf

Chandhoke, B. (2014). Get more wiggle room in your design’s RMS Phase Jitter budget

http://www.embedded.com/design/real-time-and-performance/4432619/2/Get-more-wiggle-room-in-your-design-s-RMS-Phase-Jitter-budget

Chandhoke, B. (2014). Overcoming the clock tree design challenge in EDN

http://www.edn.com/design/wireless-networking/4434901/Clock-tree-design-challenge

Chandhoke, B. (2012). CrystalFree™ Solid-State Oscillator Technology White Paper

http://www.digikey.ie/Web%20Export/Supplier%20Content/IDT_800/pdf/idt-pi-crystalfree-solid-state-oscillator.pdf

Chandhoke, B. (2011). Multi-Benefits from Multi-PLL Programmable Clocks

http://www.electronicproducts.com/Analog_Mixed_Signal_ICs/Communications_Interface/Multi_benefits_from_multi-PLL_programmable_clocks.aspx

Chandhoke, B. (2010, January 27). Understanding the different types of clock jitter. EE Times Asia.

http://www.eetasia.com/STATIC/PDF/201001/EEOL_2010JAN27_POW_TA_01.pdf?SOURCES=DOWNLOAD

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