Adel Dokhanchi

Tempe, AZ 480-***-****

http://www.public.asu.edu/~adokhanc/

acxnyu@r.postjobfree.com

Computer Engineer

Accomplished computer engineer with experience in formal verification of Cyber-Physical Systems (CPS) and Electronic Design Automation (EDA). Able to quickly adapt to ever-changing environments and to thrive in a stressful environment with tight deadlines. Experienced in problem analysis, algorithmic solutions, implementing efficient programs, and verification and validation of the results towards the desired goals.

C/C++

Verilog/VHDL

Systems Modeling and Verification

Model Checking UPPAAL/NuSMV

Matlab

Java

CPS Testing and Monitoring

Temporal Logic (LTL,MTL,TPTL)

Latex

Pascal

Formal Methods and Modeling

FPGA/VLSI CAD

Education

Ph.D. in Computer Science, Arizona State University, Tempe, AZ, 2016

M.S. in Computer Engineering, Amirkabir University of Technology, Tehran, Iran, 2008

B.S. in Computer Engineering, Shahid Beheshti University, Tehran, Iran, 2005

Professional Experience

Arizona State University, Tempe, AZ 2010-Present

Research Assistant, Testing, and Verification of Cyber-Physical Systems, 2012-Present

Assist in the development of S-TaLiRo toolbox that tests and verifies CPS for Matlab and Simulink models. Research and develop an on-line monitoring algorithm for Metric Temporal Logic (MTL) and an offline-monitoring algorithm for Timed Propositional Temporal Logic (TPTL) for Matlab and Simulink models. Create a monotonicity algorithm for multi-parameter estimation of parametric temporal logic.

Utilized the S-TaLiRo tool for computing the space and time robustness of temporal logic CPS requirements.

Designed a testing suite with the coverage estimation of Hybrid Automata for Simulink models.

Developed a specification-debugging framework to formalize the detection of errors for real-time requirements.

Researched and developed an automatic vacuous signal detection algorithm for S-Taliro falsification framework.

Embedded Systems, 2010-Present

Develop Linux character device drivers for multithread communication, which provided a number of message bus device drivers and message queues that were shared between periodic tasks as sender, daemon, and receiver.

Created a Linux Kernel module as a hashtable device file system, which was shared between multiple threads to provide operations including add, search, and delete to the hashtable in Kernel space.

Developed a processer-in-the-loop (PIL) simulation for robot control application using Simulink code generation, utilizing the target system running VxWorks RTOS and establishing the communication with Matlab host.

Devised a model-based robot controller utilizing Matlab iRobot Create simulator toolbox.

Implementing real-time scheduling protocols such as Earliest Deadline First (EDF), Rate-Monotonic (RM), and Deadline-Monotonic (DM) and compare their schedulability through statistical analysis.

Produced a robot collision avoidance controller with Simulink embedded code generation for Mindstorm NXT.

Programmed a communication application in TinyOS platform for TelosB mote wireless sensor network devices.

Programmed a GUI Java application on an Android platform for controlling a Wi-Fi connection.

Teaching Assistant, 2013, 2014, 2015

Introduction to Theoretical Computer Science.

Electronic Design Automation, VLSI EDA Related Research Projects, 2010-2011

Performed research on non-deterministic program derivation for the parallelization of CAD algorithms.

Developed an algorithm for an optimal balanced binary tree with the application for zero skew clock tree routing.

Reduced the 3SAT problem into minimum bi-sectioning to prove the NP-Completeness of circuit partitioning.

Azad University, Parand Branch, Tehran, Iran 2010

Lecturer

Taught courses on Digital Design Fundamentals and Principles of Programming with C.

Shahid Beheshti University, Tehran, Iran 2009-2010

Electronic Design Automation, FPGA CAD

Designed FPGA architecture with on-chip microwave transceiver for Radio-Frequency (RF) Interconnect.

Created and implemented a post routing interconnect optimization algorithm using RF transceiver assignments.

Amirkabir University of Technology, Tehran, Iran 2005-2008

Teaching Assistant, 2008

Logic Design.

Electronic Design Automation, VLSI CAD, 2005-2008

Researched and developed circuit retiming algorithms for post placement performance improvement. Updated the layout placement to adapt new retiming improvements in critical paths. Developed static timing analysis algorithms for the estimation of circuit delay in the physical layout.

Implemented a simulation-based power analysis algorithm for physical synthesis

Developed post-synthesis gate sizing algorithm for improvement of circuit delay.

Publications

Formal Requirement Debugging for Testing and Verification of Cyber-Physical Systems Adel Dokhanchi, Bardh Hoxha and Georgios Fainekos (under review)

An Efficient Algorithm for Monitoring Practical TPTL Specifications Adel Dokhanchi, Bardh Hoxha, Cumhur Erkan Tuncali and Georgios Fainekos (under review)

MITL Specification Debugging for Monitoring of Cyber-Physical Systems Adel Dokhanchi, Bardh Hoxha and Georgios Fainekos - Vienna, Austria – MTCPS, 2016

Mining Parametric Temporal Logic Properties in Model-Based Design for Cyber-Physical Systems Bardh Hoxha, Adel Dokhanchi and Georgios Fainekos - Accepted for publication in journal STTT

Metric Interval Temporal Logic Specification Elicitation and Debugging Adel Dokhanchi, Bardh Hoxha and Georgios Fainekos - Austin, Texas - MEMOCODE, 2015

Requirements driven falsification with coverage metrics A. Dokhanchi, A. Zutshi, R. T. Sriniva, S. Sankaranarayanan, G. Fainekos - Amsterdam, Netherlands - EMSOFT, 2015

Towards Formal Specification Visualization for Testing and Monitoring of Cyber-Physical Systems B Hoxha, H. Bach, H. Abbas, A. Dokhanchi, Y. Kobayashi and G. Fainekos - Lausanne, Switzerland - DIFTS, 2014

On-Line Monitoring for Temporal Logic Robustness Adel Dokhanchi, Bardh Hoxha and Georgios Fainekos - Toronto, Canada - RV, 2014

Demo: S-TaLiRo: A tool for Testing and Verification for Hybrid Systems: Recent Functionality and Additions B. Hoxha, H. Abbas, A. Dokhanchi, G. Fainekos - Berlin, Germany - HSCC, 2014

Performance Improvement and Congestion Reduction of Large FPGAs Using On-Chip Microwave Interconnects Mohammad Taghi Teimoori, Ali Jahanian, Adel Dokhanchi - IEICE Transactions 95-C(10): 1610-1619 (2012)

Feasibility Study of Using the RF Interconnects in Large FPGAs to Improve Routing Tracks Usage A. Dokhanchi, A. Jahanian, E. Mehrshahi, M. T. Teimoori - Chennai, India - ISVLSI, 2011

Performance Improvement of Physical Retiming with Shortcut Insertion Adel Dokhanchi, Mostafa Rezvani, Ali Jahanian, Morteza Saheb Zamani - Montpellier, France - ISVLSI, 2008

Using Shannon Decomposition for Improving Physical Design of VLSI (in Persian) A. Dokhanchi, M. Rezvani, and M. S. Zamani, The 13th International CSI Computer Conference - Kish Island, Iran - 2008.

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