Srinivas Srivasthava Balagowni

(***) *** – **** acxih2@r.postjobfree.com. 2227 Northrop Avenue, Apt #32 Sacramento CA 95825 OBJECTIVE: To obtain a Hardware/ Embedded Software/ Validation Engineer position, where I could use my academic experience and improve my skills and knowledge.

EDUCATION

M.S. in Electrical & Electronics Engineering: California State University, Sacramento, CA(Dec 2016) – GPA:3.861

B.E in Electronics and Communication Engineering: Osmania University, Hyderabad, India (2014) SKILLS

Programming Languages : C, Embedded C, MATLAB, SQL Hardware : Verilog, VHDL, System Verilog

Scripting Languages : Python, Perl, TCL

Simulators : Simulink, PSpice, VCS Verilog Simulator, Spectre RTL Synthesis Tool : Synopsys Design Compiler

FPGA’s & Version Control : Spartan 3E, DEO Nano (Cyclone IV), Git Operating Systems : Linux, Windows, Raspbian, Linux Kernel IDE : Xilinx ISE, Modelsim, Cadence Virtuoso, Mentor Graphics, Microsoft Visual Studio Others

Knowledge of Protocols - PCIe, MESI, Berkeley, I2C, Numerical Analysis – Curve fitting, regression, optimization, Design Techniques - Digital/Analog/Mixed Signal, ASIC, VLSI, CMOS, Low Power High Speed, IC Bld Blks - PLL, DAC Computing Method - Static Timing Analysis using PrimeTime COURSEWORK

Advance Topics in Logic Design Digital Integrated Circuit Design Advance Digital Design Adv. Semiconductor Devices

Micro Computer System Dsgn Analog & Mixed Signal IC Dsgn Hierarchical Digital Dsgn Key Mixed Signal IC Bld Blks ACADEMIC PROJECTS

Design, Validation and Synthesis of Floating Point ALU using Verilog and Synopsys Design Compiler

Designed a floating point ALU using Verilog which is capable of performing 32bit floating point addition and multiplication. Generated code coverage reports and synthesized the RTL code using Synopsys Design Compiler.

Implemented low power design techniques like – clock gating, Gray Code Encoding for Finite State Machines.

Used Perl script to automatically generate input testing data and output testing data. Used automation to validate the design. Design of a Combinational multiplier, hamming code, calculator LCD display, SRAM and Traffic controller using Verilog and VHDL.

Implemented a combinational multiplier using basic logic gates, half adders and full adders. Designed a calculator, which displays its output on the LED screen. Used hierarchical design methodology to implement above designs.

Used Spartan3E FPGA board to test the designs. Address and Data of SRAM are displayed on logic analyzer. Implemented Navigation of Unmanned Ground Vehicle and Home Security System Using Raspberry Pi

Built and programmed an autonomous bot that navigates using a GPS module and obstacle avoidance sensors.

Implemented home alarm system by interfacing with motion detecting sensor, buzzer and camera, using 1-wire interface and GPIO, Python coding on Raspbian Linux OS.

Analysis of the behavioral model for a fully differential 10-bit pipelined ADC.

Used the 1.5 – bit/stage architecture for the pipelined ADC, studied the effect of mismatches between the capacitors, effect of low gain & input offset voltages. Determined the functionality, ENOB, SNR, SNDR, linear and nonlinear errors.

FFTs and Histograms are generated using MATLAB code of the ADC behavioral model. Design, Simulation and Layout of the Control Logic and Counter for a 6-bit Dual-Slope Analog-to-Digital Converter in 0.18μm CMOS using Cadence Virtuoso.

Designed control logic and counter using hierarchical design methodology. Passed DRC and generated LVS report. Design and Simulation using PSpice of Latching Comparator & Operational Amplifier in 0.35μm CMOS Process.

Designed a wide swing folded cascode op-amp circuit using PSpice to simulate the designs, for DC, AC transient analysis. Design and Simulation of Cross coupled Oscillator in 0.18μm Process – designed to operate at 1GHz. WORK EXPERIENCE

Teaching Associate, Electrical and Electronic Engineering Dept., Sacramento State, CA Jan 2016 – Present Instructor of Record for Intro to Logic Dsgn & Teaching Asst. for Analog & Mixed Signal Integrated Circuit Dsgn

Note Taker, Services to Students with Disabilities, Sacramento State, CA Jan 2015 – Present

Contact this candidate