Bo Pang

626-***-****

acxg4p@r.postjobfree.com

*** ******* **** **., *** Jose, CA 95119

SUMMARY Over 4 years’ experience in semiconductor device and digital design area, new master graduate student in EE, proficient in HDL(Verilog) and HVL(SystemVerilog/UVM), highly organized and efficient in fast-paced multitasking environments, able to communicate effectively with teammates. Seeking full-time position in the domain of digital design/verification. EDUCATION Stevens Institute of Technology, Hoboken, NJ June 2016 Master of Science in Electrical Engineering Concentration: Computer Architecture Certificate: Real-Time & Embedded System GPA: 3.94/4.0 Course Work:

Digital & Computer System Architecture Introduction to VLSI Design Real-Time Embedded Systems Semiconductor Devices Physics Heterogeneous Computing Archit & Hardware Computing Princ. of Embedded System Jilin University, China June 2014

Bachelor of Electronic Science and Technology, Semiconductor Chemistry GPA: 3.66/4.0

SKILLS Verilog, SystemVerilog, UVM, Java, C, CUDA C, Perl, VHDL ModelSim, QuestaSim, VCS, Vivado, Xilinx ISE, Visual Studio, Quartus II, Tanner EDA, Matlab ACADEMIC

PROJECTS

Full-Duplex mode Serializer - Deserializer Spring 2016

● Designed a 32 bit SerDes module in Verilog, used Perl for port connection as well as correctness.

● Injected special identifiable pattern into serial data stream as clock signal for synchronization.

● Guaranteed Des clock validness with feedback between PLL and clock signal-extractor in decoder module

● Modified the design and inserted BIST function to achieve DFT. UVM verification Platform for Wishbone-Compatible SPI core Spring 2016

● Designed a wishbone-compatible SPI core module with M68HC11 Serial Peripheral Interface

● Built a complete UVM verification environment, which can run and print report automatically.

● Multiple sequences can be initiated and used simultaneously to inject different kinds of transaction. Harris Corner Detector with CUDA C Fall 2015

● Designed a Harris Corner Detector kernel running on NVidia GeForce 650M to improve performance.

● Used streaming and pinned memory to further shorten run time.

● Used OpenCV library to simplify peripheral code. FPGA-Based 5-Stage Pipeline RISC Microprocessor Fall 2015

● Designed a FPGA-based practical RISC microprocessor with 5-stage pipeline structure in Verilog.

● Used a round-robin policy bus to communicate among CPU, memory, and IO.

● Used block memory to simulate main memory and ROM, storing compiled machine code.

● Supported detecting and handling data/control hazard, and interrupt/exceptions Layout Design of Random Noise Generator & Baugh-Wooley Multiplier and SPICE Simulation Spring 2015

● Designed transistor level schematic, implemented the design to layout with L-edit, finished DRC.

● Wrote SPICE code and analyzed netlist, got the design optimized, tested the performance of project working under different temperatures and supply voltages.

● Constructed the same design in ISE with VHDL, compared the output waveform with simulation outcome from T-spice.

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