Ami E. Walker Beck

*** * ****** *****, ********, AZ 85249

480-***-****

acxda8@r.postjobfree.com

Qualifications for Senior Engineer.

Personal Profile

Technical leader with proven track record in development and high volume manufacturing environments. Strong organizational, project management, leadership, data and statistical analysis skills within multiple functional areas including planar, lithography and dry etch. Strong analytics skills with proven aptitude for data visualization utilizing large databases and statistical software.

Professional History

First Solar: Tempe, AZ: PV Plant Performance Engineer: (August 2016- Present)

Plant Performance Engineer responsible for conducting performance analysis of PV Power Plants using analytical tools to generate performance reports. Able to investigate Performance issues and data anomalies by utilizing statistical methods, plant logs and inquiries to explain and remedy the source of any issues. Strong organizational skills to ensure all new business is setup with all necessary documentation and all monthly reporting is executed flawlessly and on schedule.

Isola Corp: Chandler, AZ: Senior Process Engineer: (February 2016- June 2016)

Senior Process Engineer for printed circuit board design plant. Responsibilities included process characterization, equipment optimization and troubleshooting, and process capability reporting using statistical analysis. Utilized historical data to optimize product design for enhanced equipment settings and control.

Intel: AZFSM: Ocotillo, AZ: Senior Dry Plasma Etch Process Engineer:

(January 2013- December 2015)

Worked as a TEL Dry Etch Process Engineer within the Contact module of the process. Primary functions include tool and layer performance, daily sustaining and defect performance. One significant project was to introduce APC, automated process control, within the TEL dry etch toolset. As the project owner I created the logic needed to automate the models and set up multiple functional areas across multiple factories for multiple processes. The scope included project development through implementation in the factory as well as follow through with training and documentation for other engineers and technicians. Targeting improved by 35% and variance decreased by 28%. APC control compensated for etch effects associated with part life dependent factors as well as offsets required for product to product density differences. End of line performance targeting improved by 25%. Another example of innovation within the dry etch module was to optimize the layer sequence effect on etcher performance. Defect performance are impacted by layer sequencing. A 25% reduction in chamber related defects was achieved at the end of this project by optimizing chamber conditions by managing run order through the etcher. New part qualifications for cost reduction were routine efforts in order to maintain quality while looking for opportunities to save money. Through multiple part life extensions and new vendor part qualifications I was able to reduce cost by 65% on consumables. Model based problem solving and design of experiments are regular tools employed to develop solutions and root cause problems.

Intel: F12/32: Ocotillo, AZ: Lithography Process Engineer: (May 2007-January 2013)

Work as a Lithography layer owner across several layers and technology nodes on 248nm and 193nm platforms. Primary job functions were daily sustaining, reticle qualifications and new product introductions. I developed a website that published a matrix of which tools were qualified with passing CD and REG data by layer and product. This highlighted open paths and more importantly identified where qualifications were needed. Balancing cycle time goals and quality goals were the constant focus in order to move material through the factory. I worked with stakeholders within my organization and engaged resources from automation in order to achieve these results, which ultimately resulted in significant cycle time gains as well as organizational advantages. One example of incremental process improvement was to set up an advanced APC system that added an additional layer of control to the traditional layer/reticle/product partitioning to controlling the volume runner and allowing lower volume products to run based on characterized offsets. This enabled all products to be qualified at a layer with a single look ahead lot as well as extended metrology skip rates significantly.

Intel: F23: Colorado Springs, CO: Planar Process Engineer:

(May 2005- August 2005; July 2006- May 2007):

Planar process engineer responsible for ensuring tools were available and running on target to ensure cycle time was met. I troubleshot defect problems and applied statistical methods to evaluate the tool was operating within limits. Work on ensuring the down time was minimized so throughput was met to meet customer demands. I worked on PCS reviews and worked on any mismatches to ensure all key parameters were matched within 10%. New vendor qualification on multiple consumables to improve costs by 50%.

Education:

Colorado School of Mines: Bachelor of Science in Chemical Engineering: January 2003- June 2006: 3.7/4.0 GPA

ASU: Graduate Level: Device Physics, Photovoltaic Design and Manufacturing, Statistical Analysis

Skills:

Computer skills: JMP, Minitab, SQL, All Microsoft Office, C++

Lean Manufacturing, Model Based Problem Solving

Semiconductor Tool Experience: Planar: CMP, Lithography: TEL Lithius, Nikon: s205,s305, immersion; ASML scanner; immersion and dry. Dry etch: Telius CIPx platforms.

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