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ASIC design engineer

San Diego, California, United States
January 13, 2017

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**** ***** **, **** ***, San Diego, CA- 92122 +1 (214) ***-****


Seeking entry-level opportunity in the field of ASIC/FPGA design and verification. Education:

M. S. in Computer Engineering, Major GPA – 3.27/4.0 August 2014 – May 2016 The University of Texas, Dallas

B. Tech. in Electronics and Communications Engineering, GPA – 7.32/10 June 2010 - May 2014 Gandhi Institute of Technology and Management (GITAM University) Software/Technical Skills:

Technical Skills: Python, C, C++, System Verilog, Basics of UVM, RTL Design, Verilog, DFT, Perl, HSPICE, ARM Programming, UNIX Shell scripting, Java, SQL, TCP/IP, Hadoop, MapReduce Tools Used: Cadence- Virtuoso, Encounter, Synopsys- HSPICE, Design Compiler, PrimeTime, Xilinx, ModelSim, MATLAB, Eclipse, Visual Studio, MySQL, SimpleScalar, Wireshark, Hive, Sqoop, Pig, HBase, Kafka, Scala, Spark Relevant Coursework:

VLSI Design Advanced Digital Logic Design Analysis of Reconfigurable Systems Computer Architecture Testing and Testable Design Design Analysis of Computer Algorithms Microprocessor Systems Design Automation of VLSI Data Structures and Algorithms Digital Signal Processing Digital Design through Verilog Advanced Computer Networks Work Experience:

ASIC Design Intern at Scalable Systems Research Labs November 2016 – Present Implementing an RTL design using Verilog for the micro-architecture of a Fused Multiply add operation as a part of FPU design team.

Academic Projects:

Implementation of Pipelined Microprocessor based on RISC Architecture on FPGA January 2015 – April 2015 Using Verilog, a 16 bit custom configurable microprocessor based on RISC architecture with pipelining was designed and implemented on the Nexys-4 DDR Artix-7 FPGA Board. The design could perform various functions, from basic arithmetic operations to interrupt handling. Verilog Test Benches were used to verify this design.

Implementation of 16-bit ALU using IBM 130nm technology September 2014 – December 2014 Designed an ASIC which involved the Verilog implementation of a 16 bit ALU which was synthesized to a gate level design using Synopsys Design Vision. A standard cell library was designed while conducting Design Rule Check and Layout vs Schematic check, containing required cells using Cadence Virtuoso and Schematic. The design was placed and routed using Cadence encounter and static timing analysis was done using Synopsys Primetime.

Circuit Bi-Partitioning using Simulating Annealing September 2015 – October 2015 Using C++, designed a tool which after reading a netlist and area list, stores the cell information using data structures. Using the Simulated Annealing Algorithm, an efficient design with minimum number of wires running between the partitions is generated effectively reducing the HW going on to the PCB. The tool was compiled and implemented on UNIX platform.

Implementation of fixed die standard cell placer using Simulating Annealing November 2015 – December 2015 Using C++, designed a standard cell placer for a circuit having cells of equal size so that the wire length is minimal. Simulated Annealing Algorithm has been used to develop an efficient design with minimal wire length. The tool was compiled and implemented on UNIX platform.

Optimal Cache and Branch Predictor Configuration for ALPHA Microprocessor September 2014 – December 2014 Fine tuned the cache hierarchy of the Alpha microprocessor for 3 benchmarks - GCC, Anagram and GO using the SimpleScalar tool. Developed Perl scripts to automate the simulation and generate reports. Explored the effect of different choices of Cache Configuration and branch-predictors using SimpleScalar.

Fault Coverage and Testing of circuits using Synopsys and TetraMAX ATPG January 2016 – April 2016 For a given combinational or sequential circuit, a Verilog code was implemented, synthesized and optimized using Synopsys Design Vision. Used Synopsys ATPG to determine test vectors, Stuck at faults and fault coverage.

BIST for a 4 bit Multiplier January 2016 – April 2016 Using Verilog, designed and implemented a BIST design for testing a 4 bit Multiplier by generating pseudo random patterns using Linear Feedback Shift Register and compacting the response of Multiplier using Multiple Input Signature Register. Visa Status/Availability: F1 visa, OPT started on 27th June 2016

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