Engineering Computer

NEHA THOTAPPALA JAYAPRAKASH

**** * ******* ******, ***#K14, Fullerton, CA 92831 ***************@***.*********.*** 615-***-****

https://www.linkedin.com/in/neha-thotappala-jayaprakash

Summary

A Telecommunication engineering graduate currently pursuing masters in computer engineerin, actively seeking a summer internship opportunity.

Education

Masters in Computer Engineering Expected Graduation May 2018

California State University, Fullerton GPA:3.8

Bachelor of Technology in Telecommunication Engineering May 2015

Dayananda Sagar College of Engineering, India GPA:3.6

Technical Skills

Computer skills : C, C++, Hardware description Language/VHDL, Digital Signal Processing using MATLAB,

net, sql, html, java scripts, Visual Basics

Assembly languages : 8051 microcontroller, 8056 microprocessor.

Tools : MS Office family, Visual Studio,ASP.net

VLSI Concepts : Fault models, Automatic Test Pattern Generation,Fault Simulation, SCOAP Testability analysis,

logic simulations, logic Built-In-Self-Test, scan chain diagnosis.

Nanotechnology concepts : Micro and nano fluidics, Bulk materials, quantum dots, fabrication at nanoscale.

Work Experience

Associate Software Engineer at Accenture Private Limited August 2015-June2016

Worked in the development project of the company where we developed a tool team to reduce the manual work and automated various processes which improved overall efficiency of the team and could be used by all the employees of the company.

Resolved issues related to tickets, modified tool as and when required using sql and html,kept track of all the data entries backend, tested and debugged when error occurred.

Worked on application such as .net, wcf .

Academic Projects

Analysis for MOSCap: September 2016

This project was developed using the tool ‘ABACUS’ in nanohub where the effect of gate insulator thickness,gate insulator dieclectric constant and semiconductor thickness have on energy band,electron density and hole density for n type MOS Capacitor was noted for different regions like accumulation, depletion and inversion .

A Robustic approach against scan based attacks in secure hardware circuits October-December 2016

Cryptographic algorithms are the most efficient methods to maintain the information that is highly confidential to be transmitted between authenticated users only.In our paper, we propose a novel approach where we develop a completely exclusive security method by considering all the probabilities and strategies of hackers which not only makes attacker’s work tedious to steal the information but also increases the efficiency of our IC’s that are to be implemented. Through this method, it completely makes the work of attacker difficult because they have to pass through several layers of security by considering all probabilities and by implementing our approach. It also helps in reducing the overhead and increases the fault coverage of the circuit.

A Robustic cryptosystem using astroid curve over prime field February-May 2015

In this paper,we proposed an efficient astroid curve prime field.This public key cryptographic technique is used for secured data transmission and is highly reliable.The work includes encryption of the intelligent message at the sender and decryption of the unintelligent message at the receiver end.Our proposed work can be used as cryptographic caculator and is time efficient than the existing cryptographic methods such as RSA and ECC

Involvement & Activities

Worked as a Volunteer in Science Academics lecture workshop on Nanotechnology and Biosensors jointly organized by Indian Academy of Science(IASc), Indian National Sciences Academy(INSA).

Participated in one day workshop on “Space communication” conducted by AMSAT India

Participated in two day workshop on network implementation and security organized by Association for computer machinery-IIT Delhi

Certified LabVIEW core 1 and core 2 training organized by National Instruments and Trident Tech Labs Pvt.Ltd.

Contact this candidate